2 ******************************************************************************
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3 * @file system_stm32f10x.c
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4 * @author MCD Application Team
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7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 ******************************************************************************
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10 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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12 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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14 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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18 ******************************************************************************
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21 /** @addtogroup CMSIS
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25 /** @addtogroup stm32f10x_system
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29 /** @addtogroup STM32F10x_System_Private_Includes
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33 #include "stm32f10x.h"
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39 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
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47 /** @addtogroup STM32F10x_System_Private_Defines
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51 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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52 frequency (after reset the HSI is used as SYSCLK source)
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56 1. After each device reset the HSI is used as System clock source.
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58 2. Please make sure that the selected System clock doesn't exceed your device's
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61 3. If none of the define below is enabled, the HSI is used as System clock
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64 4. The System clock configuration functions provided within this file assume that:
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65 - For Low, Medium and High density devices an external 8MHz crystal is
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66 used to drive the System clock.
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67 - For Connectivity line devices an external 25MHz crystal is used to drive
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69 If you are using different crystal you have to adapt those functions accordingly.
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72 /* #define SYSCLK_FREQ_HSE HSE_Value */
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73 /* #define SYSCLK_FREQ_24MHz 24000000 */
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74 /* #define SYSCLK_FREQ_36MHz 36000000 */
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75 /* #define SYSCLK_FREQ_48MHz 48000000 */
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76 /* #define SYSCLK_FREQ_56MHz 56000000 */
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77 #define SYSCLK_FREQ_72MHz 72000000
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79 /*!< Uncomment the following line if you need to use external SRAM mounted
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80 on STM3210E-EVAL board (STM32 High density devices) as data memory */
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82 /* #define DATA_IN_ExtSRAM */
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83 #endif /* STM32F10X_HD */
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89 /** @addtogroup STM32F10x_System_Private_Macros
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97 /** @addtogroup STM32F10x_System_Private_Variables
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101 /*******************************************************************************
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102 * Clock Definitions
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103 *******************************************************************************/
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104 #ifdef SYSCLK_FREQ_HSE
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105 const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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106 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */
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107 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */
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108 const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */
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109 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */
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110 #elif defined SYSCLK_FREQ_24MHz
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111 const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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112 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */
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113 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */
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114 const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */
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115 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */
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116 #elif defined SYSCLK_FREQ_36MHz
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117 const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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118 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */
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119 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */
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120 const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */
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121 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */
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122 #elif defined SYSCLK_FREQ_48MHz
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123 const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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124 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */
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125 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */
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126 const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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127 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */
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128 #elif defined SYSCLK_FREQ_56MHz
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129 const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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130 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */
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131 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */
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132 const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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133 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */
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134 #elif defined SYSCLK_FREQ_72MHz
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135 const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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136 const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */
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137 const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */
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138 const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */
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139 const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */
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140 #else /*!< HSI Selected as System Clock source */
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141 const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */
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142 const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */
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143 const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */
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144 const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */
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145 const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */
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152 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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156 static void SetSysClock(void);
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158 #ifdef SYSCLK_FREQ_HSE
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159 static void SetSysClockToHSE(void);
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160 #elif defined SYSCLK_FREQ_24MHz
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161 static void SetSysClockTo24(void);
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162 #elif defined SYSCLK_FREQ_36MHz
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163 static void SetSysClockTo36(void);
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164 #elif defined SYSCLK_FREQ_48MHz
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165 static void SetSysClockTo48(void);
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166 #elif defined SYSCLK_FREQ_56MHz
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167 static void SetSysClockTo56(void);
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168 #elif defined SYSCLK_FREQ_72MHz
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169 static void SetSysClockTo72(void);
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176 /** @addtogroup STM32F10x_System_Private_Functions
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181 * @brief Setup the microcontroller system
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182 * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.
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183 * @note This function should be used only after reset.
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187 void SystemInit (void)
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189 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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190 /* Set HSION bit */
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191 RCC->CR |= (uint32_t)0x00000001;
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193 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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194 #ifndef STM32F10X_CL
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195 RCC->CFGR &= (uint32_t)0xF8FF0000;
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197 RCC->CFGR &= (uint32_t)0xF0FF0000;
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198 #endif /* STM32F10X_CL */
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200 /* Reset HSEON, CSSON and PLLON bits */
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201 RCC->CR &= (uint32_t)0xFEF6FFFF;
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203 /* Reset HSEBYP bit */
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204 RCC->CR &= (uint32_t)0xFFFBFFFF;
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206 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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207 RCC->CFGR &= (uint32_t)0xFF80FFFF;
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209 #ifndef STM32F10X_CL
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210 /* Disable all interrupts and clear pending bits */
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211 RCC->CIR = 0x009F0000;
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213 /* Reset PLL2ON and PLL3ON bits */
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214 RCC->CR &= (uint32_t)0xEBFFFFFF;
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216 /* Disable all interrupts and clear pending bits */
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217 RCC->CIR = 0x00FF0000;
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219 /* Reset CFGR2 register */
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220 RCC->CFGR2 = 0x00000000;
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221 #endif /* STM32F10X_CL */
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223 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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224 /* Configure the Flash Latency cycles and enable prefetch buffer */
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230 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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234 static void SetSysClock(void)
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236 #ifdef SYSCLK_FREQ_HSE
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237 SetSysClockToHSE();
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238 #elif defined SYSCLK_FREQ_24MHz
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240 #elif defined SYSCLK_FREQ_36MHz
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242 #elif defined SYSCLK_FREQ_48MHz
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244 #elif defined SYSCLK_FREQ_56MHz
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245 SetSysClockTo56();
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246 #elif defined SYSCLK_FREQ_72MHz
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250 /* If none of the define above is enabled, the HSI is used as System clock
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251 source (default after reset) */
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255 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
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256 * before jump to __main
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260 #ifdef DATA_IN_ExtSRAM
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262 * @brief Setup the external memory controller.
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263 * Called in startup_stm32f10x_xx.s/.c before jump to main.
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264 * This function configures the external SRAM mounted on STM3210E-EVAL
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265 * board (STM32 High density devices). This SRAM will be used as program
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266 * data memory (including heap and stack).
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270 void SystemInit_ExtMemCtl(void)
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272 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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273 required, then adjust the Register Addresses */
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275 /* Enable FSMC clock */
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276 RCC->AHBENR = 0x00000114;
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278 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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279 RCC->APB2ENR = 0x000001E0;
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281 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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282 /*---------------- SRAM Address lines configuration -------------------------*/
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283 /*---------------- NOE and NWE configuration --------------------------------*/
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284 /*---------------- NE3 configuration ----------------------------------------*/
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285 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
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287 GPIOD->CRL = 0x44BB44BB;
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288 GPIOD->CRH = 0xBBBBBBBB;
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290 GPIOE->CRL = 0xB44444BB;
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291 GPIOE->CRH = 0xBBBBBBBB;
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293 GPIOF->CRL = 0x44BBBBBB;
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294 GPIOF->CRH = 0xBBBB4444;
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296 GPIOG->CRL = 0x44BBBBBB;
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297 GPIOG->CRH = 0x44444B44;
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299 /*---------------- FSMC Configuration ---------------------------------------*/
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300 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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302 FSMC_Bank1->BTCR[4] = 0x00001011;
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303 FSMC_Bank1->BTCR[5] = 0x00000200;
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305 #endif /* DATA_IN_ExtSRAM */
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307 #ifdef SYSCLK_FREQ_HSE
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309 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
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310 * and PCLK1 prescalers.
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311 * @note This function should be used only after reset.
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315 static void SetSysClockToHSE(void)
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317 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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319 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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321 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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323 /* Wait till HSE is ready and if Time out is reached exit */
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326 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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328 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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330 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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332 HSEStatus = (uint32_t)0x01;
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336 HSEStatus = (uint32_t)0x00;
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339 if (HSEStatus == (uint32_t)0x01)
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341 /* Enable Prefetch Buffer */
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342 FLASH->ACR |= FLASH_ACR_PRFTBE;
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344 /* Flash 0 wait state */
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345 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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347 #ifndef STM32F10X_CL
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348 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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350 if (HSE_Value <= 24000000)
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352 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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356 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
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358 #endif /* STM32F10X_CL */
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360 /* HCLK = SYSCLK */
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361 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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364 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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367 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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369 /* Select HSE as system clock source */
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370 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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371 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
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373 /* Wait till HSE is used as system clock source */
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374 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
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379 { /* If HSE fails to start-up, the application will have wrong clock
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380 configuration. User can add here some code to deal with this error */
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382 /* Go to infinite loop */
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388 #elif defined SYSCLK_FREQ_24MHz
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390 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
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391 * and PCLK1 prescalers.
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392 * @note This function should be used only after reset.
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396 static void SetSysClockTo24(void)
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398 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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400 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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402 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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404 /* Wait till HSE is ready and if Time out is reached exit */
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407 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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409 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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411 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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413 HSEStatus = (uint32_t)0x01;
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417 HSEStatus = (uint32_t)0x00;
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420 if (HSEStatus == (uint32_t)0x01)
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422 /* Enable Prefetch Buffer */
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423 FLASH->ACR |= FLASH_ACR_PRFTBE;
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425 /* Flash 0 wait state */
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426 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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427 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
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429 /* HCLK = SYSCLK */
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430 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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433 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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436 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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438 #ifdef STM32F10X_CL
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439 /* Configure PLLs ------------------------------------------------------*/
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440 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
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441 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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442 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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443 RCC_CFGR_PLLMULL6);
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445 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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446 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
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447 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
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448 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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449 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
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450 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
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453 RCC->CR |= RCC_CR_PLL2ON;
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454 /* Wait till PLL2 is ready */
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455 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
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459 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
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460 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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461 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
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462 #endif /* STM32F10X_CL */
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465 RCC->CR |= RCC_CR_PLLON;
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467 /* Wait till PLL is ready */
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468 while((RCC->CR & RCC_CR_PLLRDY) == 0)
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472 /* Select PLL as system clock source */
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473 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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474 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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476 /* Wait till PLL is used as system clock source */
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477 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
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482 { /* If HSE fails to start-up, the application will have wrong clock
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483 configuration. User can add here some code to deal with this error */
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485 /* Go to infinite loop */
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491 #elif defined SYSCLK_FREQ_36MHz
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493 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
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494 * and PCLK1 prescalers.
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495 * @note This function should be used only after reset.
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499 static void SetSysClockTo36(void)
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501 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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503 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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505 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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507 /* Wait till HSE is ready and if Time out is reached exit */
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510 HSEStatus = RCC->CR & RCC_CR_HSERDY;
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512 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
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514 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
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516 HSEStatus = (uint32_t)0x01;
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520 HSEStatus = (uint32_t)0x00;
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523 if (HSEStatus == (uint32_t)0x01)
\r
525 /* Enable Prefetch Buffer */
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526 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
528 /* Flash 1 wait state */
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529 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
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530 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
532 /* HCLK = SYSCLK */
\r
533 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
536 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
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539 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
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541 #ifdef STM32F10X_CL
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542 /* Configure PLLs ------------------------------------------------------*/
\r
544 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
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545 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
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546 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
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547 RCC_CFGR_PLLMULL9);
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549 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
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550 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
\r
552 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
553 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
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554 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
555 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
\r
558 RCC->CR |= RCC_CR_PLL2ON;
\r
559 /* Wait till PLL2 is ready */
\r
560 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
565 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
\r
566 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
567 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
\r
568 #endif /* STM32F10X_CL */
\r
571 RCC->CR |= RCC_CR_PLLON;
\r
573 /* Wait till PLL is ready */
\r
574 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
578 /* Select PLL as system clock source */
\r
579 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
580 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
582 /* Wait till PLL is used as system clock source */
\r
583 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
588 { /* If HSE fails to start-up, the application will have wrong clock
\r
589 configuration. User can add here some code to deal with this error */
\r
591 /* Go to infinite loop */
\r
597 #elif defined SYSCLK_FREQ_48MHz
\r
599 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
\r
600 * and PCLK1 prescalers.
\r
601 * @note This function should be used only after reset.
\r
605 static void SetSysClockTo48(void)
\r
607 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
609 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
611 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
613 /* Wait till HSE is ready and if Time out is reached exit */
\r
616 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
618 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
620 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
622 HSEStatus = (uint32_t)0x01;
\r
626 HSEStatus = (uint32_t)0x00;
\r
629 if (HSEStatus == (uint32_t)0x01)
\r
631 /* Enable Prefetch Buffer */
\r
632 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
634 /* Flash 1 wait state */
\r
635 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
636 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
\r
638 /* HCLK = SYSCLK */
\r
639 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
642 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
644 /* PCLK1 = HCLK/2 */
\r
645 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
647 #ifdef STM32F10X_CL
\r
648 /* Configure PLLs ------------------------------------------------------*/
\r
649 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
650 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
652 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
653 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
654 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
655 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
658 RCC->CR |= RCC_CR_PLL2ON;
\r
659 /* Wait till PLL2 is ready */
\r
660 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
665 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
\r
666 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
667 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
668 RCC_CFGR_PLLMULL6);
\r
670 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
\r
671 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
672 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
\r
673 #endif /* STM32F10X_CL */
\r
676 RCC->CR |= RCC_CR_PLLON;
\r
678 /* Wait till PLL is ready */
\r
679 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
683 /* Select PLL as system clock source */
\r
684 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
685 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
687 /* Wait till PLL is used as system clock source */
\r
688 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
693 { /* If HSE fails to start-up, the application will have wrong clock
\r
694 configuration. User can add here some code to deal with this error */
\r
696 /* Go to infinite loop */
\r
703 #elif defined SYSCLK_FREQ_56MHz
\r
705 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
\r
706 * and PCLK1 prescalers.
\r
707 * @note This function should be used only after reset.
\r
711 static void SetSysClockTo56(void)
\r
713 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
715 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
717 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
719 /* Wait till HSE is ready and if Time out is reached exit */
\r
722 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
724 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
726 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
728 HSEStatus = (uint32_t)0x01;
\r
732 HSEStatus = (uint32_t)0x00;
\r
735 if (HSEStatus == (uint32_t)0x01)
\r
737 /* Enable Prefetch Buffer */
\r
738 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
740 /* Flash 2 wait state */
\r
741 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
742 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
744 /* HCLK = SYSCLK */
\r
745 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
748 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
750 /* PCLK1 = HCLK/2 */
\r
751 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
753 #ifdef STM32F10X_CL
\r
754 /* Configure PLLs ------------------------------------------------------*/
\r
755 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
756 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
758 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
759 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
760 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
761 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
764 RCC->CR |= RCC_CR_PLL2ON;
\r
765 /* Wait till PLL2 is ready */
\r
766 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
771 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
\r
772 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
773 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
774 RCC_CFGR_PLLMULL7);
\r
776 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
\r
777 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
\r
778 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
\r
780 #endif /* STM32F10X_CL */
\r
783 RCC->CR |= RCC_CR_PLLON;
\r
785 /* Wait till PLL is ready */
\r
786 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
790 /* Select PLL as system clock source */
\r
791 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
792 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
794 /* Wait till PLL is used as system clock source */
\r
795 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
800 { /* If HSE fails to start-up, the application will have wrong clock
\r
801 configuration. User can add here some code to deal with this error */
\r
803 /* Go to infinite loop */
\r
810 #elif defined SYSCLK_FREQ_72MHz
\r
812 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
\r
813 * and PCLK1 prescalers.
\r
814 * @note This function should be used only after reset.
\r
818 static void SetSysClockTo72(void)
\r
820 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
\r
822 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
\r
824 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
\r
826 /* Wait till HSE is ready and if Time out is reached exit */
\r
829 HSEStatus = RCC->CR & RCC_CR_HSERDY;
\r
831 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
\r
833 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
\r
835 HSEStatus = (uint32_t)0x01;
\r
839 HSEStatus = (uint32_t)0x00;
\r
842 if (HSEStatus == (uint32_t)0x01)
\r
844 /* Enable Prefetch Buffer */
\r
845 FLASH->ACR |= FLASH_ACR_PRFTBE;
\r
847 /* Flash 2 wait state */
\r
848 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
\r
849 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
\r
852 /* HCLK = SYSCLK */
\r
853 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
\r
856 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
\r
858 /* PCLK1 = HCLK/2 */
\r
859 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
\r
861 #ifdef STM32F10X_CL
\r
862 /* Configure PLLs ------------------------------------------------------*/
\r
863 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
\r
864 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
\r
866 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
\r
867 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
\r
868 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
\r
869 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
\r
872 RCC->CR |= RCC_CR_PLL2ON;
\r
873 /* Wait till PLL2 is ready */
\r
874 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
\r
879 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
\r
880 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
\r
881 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
\r
882 RCC_CFGR_PLLMULL9);
\r
884 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
\r
885 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
\r
886 RCC_CFGR_PLLMULL));
\r
887 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
\r
888 #endif /* STM32F10X_CL */
\r
891 RCC->CR |= RCC_CR_PLLON;
\r
893 /* Wait till PLL is ready */
\r
894 while((RCC->CR & RCC_CR_PLLRDY) == 0)
\r
898 /* Select PLL as system clock source */
\r
899 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
\r
900 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
\r
902 /* Wait till PLL is used as system clock source */
\r
903 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
\r
908 { /* If HSE fails to start-up, the application will have wrong clock
\r
909 configuration. User can add here some code to deal with this error */
\r
911 /* Go to infinite loop */
\r
930 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
\r