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59 <h1>Cortex Microcontroller Software Interface Standard</h1>
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61 <p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
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62 <p align="center">Version: 1.20 - 22. May 2009</p>
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64 <p class="TinyT">Information in this file, the accompany manuals, and software is<br>
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65 Copyright © ARM Ltd.<br>All rights reserved.
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70 <p><span style="FONT-WEIGHT: bold">Revision History</span></p>
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72 <li>Version 1.00: initial release. </li>
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73 <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
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74 <li>Version 1.02: added Cortex-M0. </li>
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75 <li>Version 1.10: second review. </li>
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76 <li>Version 1.20: third review. </li>
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84 <li class="LI2"><a href="#1">About</a></li>
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85 <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
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86 <li class="LI2"><a href="#3">CMSIS Files</a></li>
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87 <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
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88 <li class="LI2"><a href="#5">CMSIS Example</a></li>
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91 <h2><a name="1"></a>About</h2>
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94 The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
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95 that are faced when software components are deployed to physical microcontroller devices based on a
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96 Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
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97 processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation
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98 with various silicon and software vendors and provides a common approach to interface to peripherals,
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99 real-time operating systems, and middleware components.
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102 <p>ARM provides as part of the CMSIS the following software layers that are
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103 available for various compiler implementations:</p>
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105 <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
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106 address definitions and helper functions to
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107 access core registers and peripherals. It defines also an device
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108 independent interface for RTOS Kernels that includes debug channel
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110 <li><strong>Middleware Access Layer:</strong> provides common methods to
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111 access peripherals for the software industry. The Middleware Access Layer
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112 is adapted by the Silicon Vendor for the device specific peripherals used
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113 by middleware components. The middleware access layer is currently in
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114 development and not yet part of this documentation</li>
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117 <p>These software layers are expanded by Silicon partners with:</p>
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119 <li><strong>Device Peripheral Access Layer</strong>: provides definitions
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120 for all device peripherals</li>
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121 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
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122 additional helper functions for peripherals</li>
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125 <p>CMSIS defines for a Cortex-Mx Microcontroller System:</p>
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127 <li style="text-align: left;">A common way to access peripheral registers
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128 and a common way to define exception vectors.</li>
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129 <li style="text-align: left;">The register names of the <strong>Core
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130 Peripherals</strong> and<strong> </strong>the names of the <strong>Core
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131 Exception Vectors</strong>.</li>
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132 <li>An device independent interface for RTOS Kernels including a debug
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134 <li style="text-align: left;">Interfaces for middleware components (TCP/IP
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135 Stack, Flash File System).</li>
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139 By using CMSIS compliant software components, the user can easier re-use template code.
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140 CMSIS is intended to enable the combination of software components from multiple middleware vendors.
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143 <h2><a name="2"></a>Coding Rules and Conventions</h2>
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146 The following section describes the coding rules and conventions used in the CMSIS
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147 implementation. It contains also information about data types and version number information.
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150 <h3>Essentials</h3>
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152 <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
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153 there are disable and enable sequences for PC-LINT inserted.</li>
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154 <li>ANSI standard data types defined in the ANSI C header file
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155 <strong><stdint.h></strong> are used.</li>
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156 <li>#define constants that include expressions must be enclosed by
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158 <li>Variables and parameters have a complete data type.</li>
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159 <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
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161 <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
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162 (which means that wait/query loops are done at other software layers such as
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163 the <strong>Middleware Access Layer</strong>).</li>
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164 <li>For each exception/interrupt there is definition for:
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166 <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
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167 (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
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168 <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
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169 <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
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173 <h3>Recommendations</h3>
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175 <p>The CMSIS recommends the following conventions for identifiers.</p>
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177 <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
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178 <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
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179 <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
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180 <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
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186 <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
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187 (<em>// comment</em>). It is assumed that the programming tools support today
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188 consistently the C++ comment style.</li>
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189 <li><strong>Function Comments</strong> provide for each function the following information:
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191 <li>one-line brief function overview.</li>
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192 <li>detailed parameter explanation.</li>
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193 <li>detailed information about return values.</li>
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194 <li>detailed description of the actual function.</li>
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196 <p><b>Doxygen Example:</b></p>
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199 * @brief Enable Interrupt in NVIC Interrupt Controller
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200 * @param IRQn interrupt number that specifies the interrupt
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202 * Enable the specified interrupt in the NVIC Interrupt Controller.
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203 * Other settings of the interrupt such as priority are not affected.
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208 <h3>Data Types and IO Type Qualifiers</h3>
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211 The <strong>Cortex-Mx HAL</strong> uses the standard types from the standard ANSI C header file
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212 <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
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213 to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
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214 debug information of peripheral registers.
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217 <table class="kt" border="0" cellpadding="0" cellspacing="0">
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220 <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
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221 <th class="kt">#define</th>
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222 <th class="kt">Description</th>
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225 <td class="kt" nowrap="nowrap">__I</td>
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226 <td class="kt">volatile const</td>
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227 <td class="kt">Read access only</td>
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230 <td class="kt" nowrap="nowrap">__O</td>
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231 <td class="kt">volatile</td>
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232 <td class="kt">Write access only</td>
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235 <td class="kt" nowrap="nowrap">__IO</td>
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236 <td class="kt">volatile</td>
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237 <td class="kt">Read and write access</td>
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242 <h3>CMSIS Version Number</h3>
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244 File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
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248 #define __CM3_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
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249 #define __CM3_CMSIS_VERSION_SUB (0x03) /* [15:0] sub version */
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250 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre>
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253 File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
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257 #define __CM0_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
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258 #define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] sub version */
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259 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre>
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262 <h3>CMSIS Cortex Core</h3>
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264 File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
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268 #define __CORTEX_M (0x03)</pre>
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271 File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-Mx with the following define:
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275 #define __CORTEX_M (0x00)</pre>
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278 <h2><a name="3"></a>CMSIS Files</h2>
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280 This section describes the Files provided in context with the CMSIS to access the Cortex-Mx
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281 hardware and peripherals.
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284 <table class="kt" border="0" cellpadding="0" cellspacing="0">
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287 <th class="kt" nowrap="nowrap">File</th>
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288 <th class="kt">Provider</th>
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289 <th class="kt">Description</th>
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292 <td class="kt" nowrap="nowrap"><i>device.h</i></td>
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293 <td class="kt">Device specific (provided by silicon partner)</td>
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294 <td class="kt">Defines the peripherals for the actual device. The file may use
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295 several other include files to define the peripherals of the actual device.</td>
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298 <td class="kt" nowrap="nowrap">core_cm0.h</td>
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299 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
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300 <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
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303 <td class="kt" nowrap="nowrap">core_cm3.h</td>
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304 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
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305 <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
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308 <td class="kt" nowrap="nowrap">core_cm0.c</td>
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309 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
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310 <td class="kt">Provides helper functions that access core registers.</td>
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313 <td class="kt" nowrap="nowrap">core_cm0.c</td>
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314 <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
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315 <td class="kt">Provides helper functions that access core registers.</td>
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318 <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
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319 <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
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320 <td class="kt">Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table</td>
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323 <td class="kt" nowrap="nowrap">system<i>_device</i></td>
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324 <td class="kt">ARM (adapted by silicon partner)</td>
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325 <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
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326 typically the oscillator (PLL) that is part of the microcontroller device</td>
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331 <h3><em>device.h</em></h3>
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334 The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
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335 <u><strong>central include file</strong></u> that the application programmer is using in
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336 the C source code. This file contains:
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340 <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
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341 (IRQn) for all core and device specific exceptions and interrupts.</p>
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344 <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
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345 actual configuration of the Cortex-Mx processor that is part of the actual
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346 device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
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347 implements access to processor registers and core peripherals. </p>
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350 <p><strong>Device Peripheral Access Layer</strong>: provides definitions
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351 for all device peripherals. It contains all data structures and the address
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352 mapping for the device specific peripherals. </p>
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354 <li><strong>Access Functions for Peripherals (optional)</strong>: provides
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355 additional helper functions for peripherals that are useful for programming
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356 of these peripherals. Access Functions may be provided as inline functions
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357 or can be extern references to a device specific library provided by the
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358 silicon vendor.</li>
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362 <h4><strong>Interrupt Number Definition</strong></h4>
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364 <p>To access the device specific interrupts the device.h file defines IRQn
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365 numbers for the complete device using a enum typedef as shown below:</p>
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369 /****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
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370 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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371 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
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372 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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373 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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374 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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375 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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376 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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377 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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378 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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379 /****** STM32 specific Interrupt Numbers ****************************************************************/
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380 WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
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381 PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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387 <h4>Configuration for core_cm0.h / core_cm3.h</h4>
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389 The Cortex-Mx core configuration options which are defined for each device implementation. Some
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390 configuration options are reflected in the CMSIS layer using the #define settings described below.
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393 To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
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394 Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
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395 defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong>
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396 preprocessor command.
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399 <table class="kt" border="0" cellpadding="0" cellspacing="0">
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402 <th class="kt" nowrap="nowrap">#define</th>
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403 <th class="kt" nowrap="nowrap">File</th>
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404 <th class="kt" nowrap="nowrap">Value</th>
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405 <th class="kt">Description</th>
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408 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
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409 <td class="kt">core_cm0.h</td>
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410 <td class="kt" nowrap="nowrap">(2)</td>
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411 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
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414 <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
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415 <td class="kt">core_cm3.h</td>
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416 <td class="kt" nowrap="nowrap">(2 ... 8)</td>
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417 <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
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420 <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
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421 <td class="kt">core_cm0.h, core_cm3.h</td>
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422 <td class="kt" nowrap="nowrap">(0, 1)</td>
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423 <td class="kt">Defines if an MPU is present or not</td>
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426 <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
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427 <td class="kt">core_cm0.h, core_cm3.h</td>
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428 <td class="kt" nowrap="nowrap">(1)</td>
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429 <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
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430 in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
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431 file must contain a vendor specific implementation of this function.</td>
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437 <h4>Device Peripheral Access Layer</h4>
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439 Each peripheral uses a <strong>PERIPHERAL_</strong> prefix to identify peripheral registers
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440 and functions that access this specific peripheral. If more than one peripheral of the same
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441 type exists, identifiers have a postfix (digit or letter). For example:
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444 <li>UART_Type: defines the generic register layout for all UART channels in a device.</li>
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445 <li>UART1: is a pointer to a register structure that refers to a specific UART.
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446 For example UART1->DR is the data register of UART1.</li>
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447 <li>UART_SendChar(UART1, c): is a generic function that works with all UART's in the device.
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448 To communicate the UART that it accesses the first parameter is a pointer to the actual
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449 UART register structure.</li>
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450 <li>UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).</li>
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453 <h5>Minimal Requiements</h5>
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455 To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
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456 and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
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459 <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
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460 Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
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461 the peripheral registers. For example:
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464 __IO uint32_t CTRL; /* SysTick Control and Status Register */
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465 __IO uint32_t LOAD; /* SysTick Reload Value Register */
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466 __IO uint32_t VAL; /* SysTick Current Value Register */
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467 __I uint32_t CALIB; /* SysTick Calibration Register */
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468 } SysTick_Type;</pre>
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471 <li><strong>Base Address</strong> for each peripheral (in case of multiple peripherals
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472 that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
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474 #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
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477 <li><strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
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478 the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. UART0,
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479 UART1). For Example:
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481 #define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
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486 These definitions allow to access the peripheral registers from user code with simple assignments like:
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488 <pre>SysTick->CTRL = 0;</pre>
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490 <h5>Optional Features</h5>
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491 <p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
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493 <li>#define constants that simplify access to the peripheral registers.
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494 These constant define bit-positions or other specific patterns are that
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495 required for the programming of the peripheral registers. The identifiers
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496 used start with the name of the <strong>PERIPERHAL_</strong>. It is
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497 recommended to use CAPITAL letters for such #define constants.</li>
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498 <li>Functions that perform more complex functions with the peripheral (i.e.
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499 status query before a sending register is accessed). Again these function
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500 start with the name of the <strong>PERIPHERAL_</strong>. </li>
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503 <h3>core_cm0.h and core_cm0.c</h3>
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505 File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
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506 the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
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507 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
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510 File <b>core_cm0.c</b> defines several helper functions that access processor registers.
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512 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
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514 <h3>core_cm3.h and core_cm3.c</h3>
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516 File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
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517 the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
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518 and core peripherals with efficient functions (defined as <strong>static inline</strong>).
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521 File <b>core_cm3.c</b> defines several helper functions that access processor registers.
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523 <p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
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525 <h3>startup_<em>device</em></h3>
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527 A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
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528 compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
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529 interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
\r
530 to an dummy handler. Therefore the interrupt handler can be directly used in application software
\r
531 without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
\r
534 The following exception names are fixed and define the start of the vector table for a Cortex-M0:
\r
537 __Vectors DCD __initial_sp ; Top of Stack
\r
538 DCD Reset_Handler ; Reset Handler
\r
539 DCD NMI_Handler ; NMI Handler
\r
540 DCD HardFault_Handler ; Hard Fault Handler
\r
548 DCD SVC_Handler ; SVCall Handler
\r
551 DCD PendSV_Handler ; PendSV Handler
\r
552 DCD SysTick_Handler ; SysTick Handler</pre>
\r
555 The following exception names are fixed and define the start of the vector table for a Cortex-M3:
\r
558 __Vectors DCD __initial_sp ; Top of Stack
\r
559 DCD Reset_Handler ; Reset Handler
\r
560 DCD NMI_Handler ; NMI Handler
\r
561 DCD HardFault_Handler ; Hard Fault Handler
\r
562 DCD MemManage_Handler ; MPU Fault Handler
\r
563 DCD BusFault_Handler ; Bus Fault Handler
\r
564 DCD UsageFault_Handler ; Usage Fault Handler
\r
569 DCD SVC_Handler ; SVCall Handler
\r
570 DCD DebugMon_Handler ; Debug Monitor Handler
\r
572 DCD PendSV_Handler ; PendSV Handler
\r
573 DCD SysTick_Handler ; SysTick Handler</pre>
\r
576 In the following examples for device specific interrupts are shown:
\r
579 ; External Interrupts
\r
580 DCD WWDG_IRQHandler ; Window Watchdog
\r
581 DCD PVD_IRQHandler ; PVD through EXTI Line detect
\r
582 DCD TAMPER_IRQHandler ; Tamper</pre>
\r
585 Device specific interrupts must have a dummy function that can be overwritten in user code.
\r
586 Below is an example for this dummy function.
\r
589 Default_Handler PROC
\r
590 EXPORT WWDG_IRQHandler [WEAK]
\r
591 EXPORT PVD_IRQHandler [WEAK]
\r
592 EXPORT TAMPER_IRQHandler [WEAK]
\r
604 The user application may simply define an interrupt handler function by using the handler name
\r
608 void WWDG_IRQHandler(void)
\r
615 <h3><a name="4"></a>system_<em>device</em>.c</h3>
\r
617 A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
\r
618 the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
\r
619 this file must provide a device specific system configuration function and a global variable
\r
620 that contains the system frequency. It configures the device and initializes typically the
\r
621 oscillator (PLL) that is part of the microcontroller device.
\r
624 The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
\r
625 as a minimum requirement the SystemInit function as shown below.
\r
628 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
631 <th class="kt">Function Definition</th>
\r
632 <th class="kt">Description</th>
\r
635 <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
\r
636 <td class="kt">Setup the microcontroller system. Typically this function configures the
\r
637 oscillator (PLL) that is part of the microcontroller device. For systems
\r
638 with variable clock speed it also updates the variable SystemFrequency.</td>
\r
644 Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
\r
645 is the variable <strong>SystemFrequency</strong> which contains the current CPU clock speed shown below.
\r
648 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
651 <th class="kt">Variable Definition</th>
\r
652 <th class="kt">Description</th>
\r
655 <td class="kt" nowrap="nowrap">uint32_t SystemFrequency</td>
\r
656 <td class="kt">Contains the system frequency (which is the system clock frequency supplied
\r
657 to the SysTick timer and the processor core clock). This variable can be
\r
658 used by the user application after the call to the function SystemInit()
\r
659 to setup the SysTick timer or configure other parameters. It may also be
\r
660 used by debugger to query the frequency of the debug timer or configure
\r
661 the trace clock speed.<br><br>
\r
662 This variable may also be defined in the <strong>const</strong> space.
\r
663 The compiler must be configured to avoid the removal of this variable in
\r
664 case that the application program is not using it. It is important for
\r
665 debug systems that the variable is physically present in memory so that
\r
666 it can be examined to configure the debugger.</td>
\r
671 <p class="Note">Note</p>
\r
673 <li><p>The above definitions are the minimum requirements for the file <strong>
\r
674 system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
\r
675 file may export more functions or variables that provide a more flexible
\r
676 configuration of the microcontroller system.</p>
\r
681 <h2>Core Peripheral Access Layer</h2>
\r
683 <h3>Cortex-Mx Core Register Access</h3>
\r
685 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
\r
686 and provide access to Cortex-Mx core registers.
\r
689 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
692 <th class="kt">Function Definition</th>
\r
693 <th class="kt">Core</th>
\r
694 <th class="kt">Core Register</th>
\r
695 <th class="kt">Description</th>
\r
698 <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
\r
699 <td class="kt">M0, M3</td>
\r
700 <td class="kt">PRIMASK = 0</td>
\r
701 <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
\r
705 <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
\r
706 <td class="kt">M0, M3</td>
\r
707 <td class="kt">PRIMASK = 1</td>
\r
708 <td class="kt">Global Interrupt disable (using the instruction <strong>
\r
709 CPSID i</strong>)</td>
\r
712 <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
\r
713 <td class="kt">M0, M3</td>
\r
714 <td class="kt">PRIMASK = value</td>
\r
715 <td class="kt">Assign value to Priority Mask Register (using the instruction
\r
716 <strong>MSR</strong>)</td>
\r
719 <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
\r
720 <td class="kt">M0, M3</td>
\r
721 <td class="kt">return PRIMASK</td>
\r
722 <td class="kt">Return Priority Mask Register (using the instruction
\r
723 <strong>MRS</strong>)</td>
\r
726 <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
\r
727 <td class="kt">M3</td>
\r
728 <td class="kt">FAULTMASK = 0</td>
\r
729 <td class="kt">Global Fault exception and Interrupt enable (using the
\r
730 instruction <strong>CPSIE
\r
734 <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
\r
735 <td class="kt">M3</td>
\r
736 <td class="kt">FAULTMASK = 1</td>
\r
737 <td class="kt">Global Fault exception and Interrupt disable (using the
\r
738 instruction <strong>CPSID f</strong>)</td>
\r
741 <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
\r
742 <td class="kt">M3</td>
\r
743 <td class="kt">FAULTMASK = value</td>
\r
744 <td class="kt">Assign value to Fault Mask Register (using the instruction
\r
745 <strong>MSR</strong>)</td>
\r
748 <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
\r
749 <td class="kt">M3</td>
\r
750 <td class="kt">return FAULTMASK</td>
\r
751 <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
\r
754 <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
\r
755 <td class="kt">M3</td>
\r
756 <td class="kt">BASEPRI = value</td>
\r
757 <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
\r
760 <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
\r
761 <td class="kt">M3</td>
\r
762 <td class="kt">return BASEPRI</td>
\r
763 <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
\r
766 <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
\r
767 <td class="kt">M0, M3</td>
\r
768 <td class="kt">CONTROL = value</td>
\r
769 <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
\r
772 <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
\r
773 <td class="kt">M0, M3</td>
\r
774 <td class="kt">return CONTROL</td>
\r
775 <td class="kt">Return Control Register Value (using the instruction
\r
776 <strong>MRS</strong>)</td>
\r
779 <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
\r
780 <td class="kt">M0, M3</td>
\r
781 <td class="kt">PSP = TopOfProcStack</td>
\r
782 <td class="kt">Set Process Stack Pointer value (using the instruction
\r
783 <strong>MSR</strong>)</td>
\r
786 <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
\r
787 <td class="kt">M0, M3</td>
\r
788 <td class="kt">return PSP</td>
\r
789 <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
\r
792 <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
\r
793 <td class="kt">M0, M3</td>
\r
794 <td class="kt">MSP = TopOfMainStack</td>
\r
795 <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
\r
798 <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
\r
799 <td class="kt">M0, M3</td>
\r
800 <td class="kt">return MSP</td>
\r
801 <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
\r
806 <h3>Cortex-Mx Instruction Access</h3>
\r
808 The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
\r
809 generate specific Cortex-Mx instructions. The functions are implemented in the file
\r
810 <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
\r
813 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
816 <th class="kt">Name</th>
\r
817 <th class="kt">Core</th>
\r
818 <th class="kt">Generated CPU Instruction</th>
\r
819 <th class="kt">Description</th>
\r
822 <td class="kt" nowrap="nowrap">void __WFI (void)</td>
\r
823 <td class="kt">M0, M3</td>
\r
824 <td class="kt">WFI</td>
\r
825 <td class="kt">Wait for Interrupt</td>
\r
828 <td class="kt" nowrap="nowrap">void __WFE (void)</td>
\r
829 <td class="kt">M0, M3</td>
\r
830 <td class="kt">WFE</td>
\r
831 <td class="kt">Wait for Event</td>
\r
834 <td class="kt" nowrap="nowrap">void __SEV (void)</td>
\r
835 <td class="kt">M0, M3</td>
\r
836 <td class="kt">SEV</td>
\r
837 <td class="kt">Set Event</td>
\r
840 <td class="kt" nowrap="nowrap">void __ISB (void)</td>
\r
841 <td class="kt">M0, M3</td>
\r
842 <td class="kt">ISB</td>
\r
843 <td class="kt">Instruction Synchronization Barrier</td>
\r
846 <td class="kt" nowrap="nowrap">void __DSB (void)</td>
\r
847 <td class="kt">M0, M3</td>
\r
848 <td class="kt">DSB</td>
\r
849 <td class="kt">Data Synchronization Barrier</td>
\r
852 <td class="kt" nowrap="nowrap">void __DMB (void)</td>
\r
853 <td class="kt">M0, M3</td>
\r
854 <td class="kt">DMB</td>
\r
855 <td class="kt">Data Memory Barrier</td>
\r
858 <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
\r
859 <td class="kt">M0, M3</td>
\r
860 <td class="kt">REV</td>
\r
861 <td class="kt">Reverse byte order in integer value.</td>
\r
864 <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
\r
865 <td class="kt">M0, M3</td>
\r
866 <td class="kt">REV16</td>
\r
867 <td class="kt">Reverse byte order in unsigned short value. </td>
\r
870 <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
\r
871 <td class="kt">M0, M3</td>
\r
872 <td class="kt">REVSH</td>
\r
873 <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
\r
876 <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
\r
877 <td class="kt">M3</td>
\r
878 <td class="kt">RBIT</td>
\r
879 <td class="kt">Reverse bit order of value</td>
\r
882 <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
\r
883 <td class="kt">M3</td>
\r
884 <td class="kt">LDREXB</td>
\r
885 <td class="kt">Load exclusive byte</td>
\r
888 <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
\r
889 <td class="kt">M3</td>
\r
890 <td class="kt">LDREXH</td>
\r
891 <td class="kt">Load exclusive half-word</td>
\r
894 <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
\r
895 <td class="kt">M3</td>
\r
896 <td class="kt">LDREXW</td>
\r
897 <td class="kt">Load exclusive word</td>
\r
900 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
\r
901 <td class="kt">M3</td>
\r
902 <td class="kt">STREXB</td>
\r
903 <td class="kt">Store exclusive byte</td>
\r
906 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
\r
907 <td class="kt">M3</td>
\r
908 <td class="kt">STREXH</td>
\r
909 <td class="kt">Store exclusive half-word</td>
\r
912 <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
\r
913 <td class="kt">M3</td>
\r
914 <td class="kt">STREXW</td>
\r
915 <td class="kt">Store exclusive word</td>
\r
918 <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
\r
919 <td class="kt">M3</td>
\r
920 <td class="kt">CLREX</td>
\r
921 <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
\r
927 <h3>NVIC Access Functions</h3>
\r
929 The CMSIS provides access to the NVIC via the register interface structure and several helper
\r
930 functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
\r
931 identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
\r
932 IRQn values are used for processor core exceptions.
\r
935 For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
\r
936 the following enum names.
\r
939 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
942 <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
\r
943 <th class="kt">Core</th>
\r
944 <th class="kt">IRQn</th>
\r
945 <th class="kt">Description</th>
\r
948 <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
\r
949 <td class="kt">M0, M3</td>
\r
950 <td class="kt">-14</td>
\r
951 <td class="kt">Cortex-Mx Non Maskable Interrupt</td>
\r
954 <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
\r
955 <td class="kt">M0, M3</td>
\r
956 <td class="kt">-13</td>
\r
957 <td class="kt">Cortex-Mx Hard Fault Interrupt</td>
\r
960 <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
\r
961 <td class="kt">M3</td>
\r
962 <td class="kt">-12</td>
\r
963 <td class="kt">Cortex-Mx Memory Management Interrupt</td>
\r
966 <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
\r
967 <td class="kt">M3</td>
\r
968 <td class="kt">-11</td>
\r
969 <td class="kt">Cortex-Mx Bus Fault Interrupt</td>
\r
972 <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
\r
973 <td class="kt">M3</td>
\r
974 <td class="kt">-10</td>
\r
975 <td class="kt">Cortex-Mx Usage Fault Interrupt</td>
\r
978 <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
\r
979 <td class="kt">M0, M3</td>
\r
980 <td class="kt">-5</td>
\r
981 <td class="kt">Cortex-Mx SV Call Interrupt </td>
\r
984 <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
\r
985 <td class="kt">M3</td>
\r
986 <td class="kt">-4</td>
\r
987 <td class="kt">Cortex-Mx Debug Monitor Interrupt</td>
\r
990 <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
\r
991 <td class="kt">M0, M3</td>
\r
992 <td class="kt">-2</td>
\r
993 <td class="kt">Cortex-Mx Pend SV Interrupt</td>
\r
996 <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
\r
997 <td class="kt">M0, M3</td>
\r
998 <td class="kt">-1</td>
\r
999 <td class="kt">Cortex-Mx System Tick Interrupt</td>
\r
1004 <p>The following functions simplify the setup of the NVIC.
\r
1005 The functions are defined as <strong>static inline</strong>.</p>
\r
1007 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1010 <th class="kt" nowrap="nowrap">Name</th>
\r
1011 <th class="kt">Core</th>
\r
1012 <th class="kt">Parameter</th>
\r
1013 <th class="kt">Description</th>
\r
1016 <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
\r
1017 <td class="kt">M3</td>
\r
1018 <td class="kt">Priority Grouping Value</td>
\r
1019 <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
\r
1022 <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
\r
1023 <td class="kt">M0, M3</td>
\r
1024 <td class="kt">IRQ Number</td>
\r
1025 <td class="kt">Enable IRQn</td>
\r
1028 <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
\r
1029 <td class="kt">M0, M3</td>
\r
1030 <td class="kt">IRQ Number</td>
\r
1031 <td class="kt">Disable IRQn</td>
\r
1034 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
\r
1035 <td class="kt">M0, M3</td>
\r
1036 <td class="kt">IRQ Number</td>
\r
1037 <td class="kt">Return 1 if IRQn is pending else 0</td>
\r
1040 <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
\r
1041 <td class="kt">M0, M3</td>
\r
1042 <td class="kt">IRQ Number</td>
\r
1043 <td class="kt">Set IRQn Pending</td>
\r
1046 <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
\r
1047 <td class="kt">M0, M3</td>
\r
1048 <td class="kt">IRQ Number</td>
\r
1049 <td class="kt">Clear IRQn Pending Status</td>
\r
1052 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
\r
1053 <td class="kt">M3</td>
\r
1054 <td class="kt">IRQ Number</td>
\r
1055 <td class="kt">Return 1 if IRQn is active else 0</td>
\r
1058 <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
\r
1059 <td class="kt">M0, M3</td>
\r
1060 <td class="kt">IRQ Number, Priority</td>
\r
1061 <td class="kt">Set Priority for IRQn<br>
\r
1062 (not threadsafe for Cortex-M0)</td>
\r
1065 <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
\r
1066 <td class="kt">M0, M3</td>
\r
1067 <td class="kt">IRQ Number</td>
\r
1068 <td class="kt">Get Priority for IRQn</td>
\r
1071 <!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
\r
1072 <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
\r
1073 <td class="kt">M3</td>
\r
1074 <td class="kt">IRQ Number, Priority Group, Preemtive Priority, Sub Priority</td>
\r
1075 <td class="kt">Encode priority for given group, preemtive and sub priority</td>
\r
1077 <!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
\r
1078 <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
\r
1079 <td class="kt">M3</td>
\r
1080 <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemtive Priority, pointer to Sub Priority</td>
\r
1081 <td class="kt">Deccode given priority to group, preemtive and sub priority</td>
\r
1084 <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
\r
1085 <td class="kt">M0, M3</td>
\r
1086 <td class="kt">(void)</td>
\r
1087 <td class="kt">Resets the System</td>
\r
1091 <p class="Note">Note</p>
\r
1093 <li><p>The processor exceptions have negative enum values. Device specific interrupts
\r
1094 have positive enum values and start with 0. The values are defined in
\r
1095 <b><em>device.h</em></b> file.
\r
1098 <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
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1099 used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
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1100 depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
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1106 <h3>SysTick Configuration Function</h3>
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1108 <p>The following function is used to configure the SysTick timer and start the
\r
1109 SysTick interrupt.</p>
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1111 <table class="kt" border="0" cellpadding="0" cellspacing="0">
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1114 <th class="kt" nowrap="nowrap">Name</th>
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1115 <th class="kt">Parameter</th>
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1116 <th class="kt">Description</th>
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1119 <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
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1120 (uint32_t ticks)</span></td>
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1121 <td class="kt">ticks is SysTick counter reload value</td>
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1122 <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
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1123 call the SysTick timer creates interrupts with the specified time
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1126 Return: 0 when successful, 1 on failure.<br>
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1133 <h3>Cortex-M3 ITM Debug Access</h3>
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1135 <p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
\r
1136 provides together with the Serial Viewer Output trace capabilities for the
\r
1137 microcontroller system. The ITM has 32 communication channels; two ITM
\r
1138 communication channels are used by CMSIS to output the following information:</p>
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1140 <li>ITM Channel 0: implements the <strong>ITM_putchar</strong> function
\r
1141 which can be used for printf-style output via the debug interface.</li>
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1142 <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
\r
1143 kernel awareness debugging.</li>
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1145 <p class="Note">Note</p>
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1147 <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
\r
1148 may use the Privileged level for program execution. ITM
\r
1149 channels have 4 groups with 8 channels each, whereby each group can be
\r
1150 configured for access rights in the Unprivileged level. The ITM channel 0
\r
1151 may be therefore enabled for the user task whereas ITM channel 31 may be
\r
1152 accessible only in Privileged level from the RTOS kernel itself.</p>
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1156 <p>The prototype of the <strong>ITM_putchar</strong> routine is shown in the
\r
1159 <table class="kt" border="0" cellpadding="0" cellspacing="0">
\r
1162 <th class="kt" nowrap="nowrap">Name</th>
\r
1163 <th class="kt">Parameter</th>
\r
1164 <th class="kt">Description</th>
\r
1167 <td class="kt" nowrap="nowrap">void uint32_t ITM_putchar(uint32_t chr)</td>
\r
1168 <td class="kt">character to output</td>
\r
1169 <td class="kt">The function outputs a character via the ITM channel 0. The
\r
1170 function returns when no debugger is connected that has booked the
\r
1171 output. It is blocking when a debugger is connected, but the
\r
1172 previous character send is not transmitted. <br><br>
\r
1173 Return: the input character 'chr'.</td>
\r
1180 Example for the usage of the ITM Channel 31 for RTOS Kernels:
\r
1183 // check if debugger connected and ITM channel enabled for tracing
\r
1184 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
\r
1185 (ITM->TCR & ITM_TCR_ITMENA) &&
\r
1186 (ITM->TER & (1UL << 31))) {
\r
1187 // transmit trace data
\r
1188 while (ITM->PORT31_U32 == 0);
\r
1189 ITM->PORT[31].u8 = task_id; // id of next task
\r
1190 while (ITM->PORT[31].u32 == 0);
\r
1191 ITM->PORT[31].u32 = task_status; // status information
\r
1195 <h2><a name="5"></a>CMSIS Example</h2>
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1197 The following section shows a typical example for using the CMSIS layer in user applications.
\r
1200 #include <device.h> // file name depends on the device used.
\r
1202 void SysTick_Handler (void) { // SysTick Interrupt Handler
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1206 void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
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1210 void timer1_init(int frequency) {
\r
1211 // set up Timer (device specific)
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1212 NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
\r
1213 NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
\r
1216 void main (void) {
\r
1219 if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
\r
1225 timer1_init (); // device specific timer
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projects / arduino / blob