2 ******************************************************************************
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3 * @file stm32f10x_rcc.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the RCC firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_rcc.h"
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24 /** @addtogroup STM32F10x_StdPeriph_Driver
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29 * @brief RCC driver modules
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33 /** @defgroup RCC_Private_TypesDefinitions
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41 /** @defgroup RCC_Private_Defines
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45 /* ------------ RCC registers bit address in the alias region ----------- */
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46 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
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48 /* --- CR Register ---*/
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50 /* Alias word address of HSION bit */
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51 #define CR_OFFSET (RCC_OFFSET + 0x00)
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52 #define HSION_BitNumber 0x00
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53 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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55 /* Alias word address of PLLON bit */
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56 #define PLLON_BitNumber 0x18
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57 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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60 /* Alias word address of PLL2ON bit */
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61 #define PLL2ON_BitNumber 0x1A
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62 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
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64 /* Alias word address of PLL3ON bit */
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65 #define PLL3ON_BitNumber 0x1C
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66 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
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67 #endif /* STM32F10X_CL */
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69 /* Alias word address of CSSON bit */
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70 #define CSSON_BitNumber 0x13
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71 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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73 /* --- CFGR Register ---*/
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75 /* Alias word address of USBPRE bit */
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76 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
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78 #ifndef STM32F10X_CL
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79 #define USBPRE_BitNumber 0x16
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80 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
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82 #define OTGFSPRE_BitNumber 0x16
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83 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
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84 #endif /* STM32F10X_CL */
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86 /* --- BDCR Register ---*/
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88 /* Alias word address of RTCEN bit */
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89 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
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90 #define RTCEN_BitNumber 0x0F
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91 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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93 /* Alias word address of BDRST bit */
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94 #define BDRST_BitNumber 0x10
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95 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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97 /* --- CSR Register ---*/
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99 /* Alias word address of LSION bit */
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100 #define CSR_OFFSET (RCC_OFFSET + 0x24)
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101 #define LSION_BitNumber 0x00
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102 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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104 #ifdef STM32F10X_CL
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105 /* --- CFGR2 Register ---*/
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107 /* Alias word address of I2S2SRC bit */
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108 #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
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109 #define I2S2SRC_BitNumber 0x11
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110 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
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112 /* Alias word address of I2S3SRC bit */
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113 #define I2S3SRC_BitNumber 0x12
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114 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
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115 #endif /* STM32F10X_CL */
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117 /* ---------------------- RCC registers bit mask ------------------------ */
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119 /* CR register bit mask */
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120 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
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121 #define CR_HSEBYP_Set ((uint32_t)0x00040000)
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122 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
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123 #define CR_HSEON_Set ((uint32_t)0x00010000)
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124 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
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126 /* CFGR register bit mask */
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127 #ifndef STM32F10X_CL
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128 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
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130 #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
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131 #endif /* STM32F10X_CL */
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133 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
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134 #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
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135 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
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136 #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
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137 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
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138 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
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139 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
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140 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
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141 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
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142 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
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143 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
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144 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
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145 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
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147 /* CSR register bit mask */
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148 #define CSR_RMVF_Set ((uint32_t)0x01000000)
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150 #ifdef STM32F10X_CL
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151 /* CFGR2 register bit mask */
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152 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
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153 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
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154 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
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155 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
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156 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
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157 #endif /* STM32F10X_CL */
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159 /* RCC Flag Mask */
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160 #define FLAG_Mask ((uint8_t)0x1F)
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163 /* Typical Value of the HSI in Hz */
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164 #define HSI_Value ((uint32_t)8000000)
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165 #endif /* HSI_Value */
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167 /* CIR register byte 2 (Bits[15:8]) base address */
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168 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
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170 /* CIR register byte 3 (Bits[23:16]) base address */
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171 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
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173 /* CFGR register byte 4 (Bits[31:24]) base address */
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174 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
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176 /* BDCR register base address */
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177 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
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179 #ifndef HSEStartUp_TimeOut
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180 /* Time out for HSE start up */
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181 #define HSEStartUp_TimeOut ((uint16_t)0x0500)
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182 #endif /* HSEStartUp_TimeOut */
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188 /** @defgroup RCC_Private_Macros
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196 /** @defgroup RCC_Private_Variables
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200 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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201 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
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207 /** @defgroup RCC_Private_FunctionPrototypes
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215 /** @defgroup RCC_Private_Functions
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220 * @brief Resets the RCC clock configuration to the default reset state.
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224 void RCC_DeInit(void)
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226 /* Set HSION bit */
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227 RCC->CR |= (uint32_t)0x00000001;
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229 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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230 #ifndef STM32F10X_CL
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231 RCC->CFGR &= (uint32_t)0xF8FF0000;
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233 RCC->CFGR &= (uint32_t)0xF0FF0000;
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234 #endif /* STM32F10X_CL */
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236 /* Reset HSEON, CSSON and PLLON bits */
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237 RCC->CR &= (uint32_t)0xFEF6FFFF;
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239 /* Reset HSEBYP bit */
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240 RCC->CR &= (uint32_t)0xFFFBFFFF;
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242 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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243 RCC->CFGR &= (uint32_t)0xFF80FFFF;
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245 #ifndef STM32F10X_CL
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246 /* Disable all interrupts and clear pending bits */
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247 RCC->CIR = 0x009F0000;
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249 /* Reset PLL2ON and PLL3ON bits */
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250 RCC->CR &= (uint32_t)0xEBFFFFFF;
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252 /* Disable all interrupts and clear pending bits */
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253 RCC->CIR = 0x00FF0000;
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255 /* Reset CFGR2 register */
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256 RCC->CFGR2 = 0x00000000;
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257 #endif /* STM32F10X_CL */
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261 * @brief Configures the External High Speed oscillator (HSE).
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262 * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
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263 * @param RCC_HSE: specifies the new state of the HSE.
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264 * This parameter can be one of the following values:
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265 * @arg RCC_HSE_OFF: HSE oscillator OFF
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266 * @arg RCC_HSE_ON: HSE oscillator ON
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267 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
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270 void RCC_HSEConfig(uint32_t RCC_HSE)
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272 /* Check the parameters */
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273 assert_param(IS_RCC_HSE(RCC_HSE));
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274 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
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275 /* Reset HSEON bit */
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276 RCC->CR &= CR_HSEON_Reset;
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277 /* Reset HSEBYP bit */
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278 RCC->CR &= CR_HSEBYP_Reset;
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279 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
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283 /* Set HSEON bit */
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284 RCC->CR |= CR_HSEON_Set;
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287 case RCC_HSE_Bypass:
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288 /* Set HSEBYP and HSEON bits */
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289 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
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298 * @brief Waits for HSE start-up.
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300 * @retval An ErrorStatus enumuration value:
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301 * - SUCCESS: HSE oscillator is stable and ready to use
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302 * - ERROR: HSE oscillator not yet ready
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304 ErrorStatus RCC_WaitForHSEStartUp(void)
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306 __IO uint32_t StartUpCounter = 0;
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307 ErrorStatus status = ERROR;
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308 FlagStatus HSEStatus = RESET;
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310 /* Wait till HSE is ready and if Time out is reached exit */
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313 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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315 } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));
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317 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
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329 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
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330 * @param HSICalibrationValue: specifies the calibration trimming value.
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331 * This parameter must be a number between 0 and 0x1F.
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334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
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336 uint32_t tmpreg = 0;
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337 /* Check the parameters */
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338 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
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340 /* Clear HSITRIM[4:0] bits */
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341 tmpreg &= CR_HSITRIM_Mask;
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342 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
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343 tmpreg |= (uint32_t)HSICalibrationValue << 3;
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344 /* Store the new value */
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349 * @brief Enables or disables the Internal High Speed oscillator (HSI).
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350 * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
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351 * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
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354 void RCC_HSICmd(FunctionalState NewState)
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356 /* Check the parameters */
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357 assert_param(IS_FUNCTIONAL_STATE(NewState));
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358 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
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362 * @brief Configures the PLL clock source and multiplication factor.
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363 * @note This function must be used only when the PLL is disabled.
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364 * @param RCC_PLLSource: specifies the PLL entry clock source.
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365 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
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366 * following values:
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367 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
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368 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
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369 * For @b other_STM32_devices, this parameter can be one of the following values:
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370 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
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371 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
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372 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
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373 * @param RCC_PLLMul: specifies the PLL multiplication factor.
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374 * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
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375 * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
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378 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
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380 uint32_t tmpreg = 0;
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382 /* Check the parameters */
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383 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
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384 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
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386 tmpreg = RCC->CFGR;
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387 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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388 tmpreg &= CFGR_PLL_Mask;
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389 /* Set the PLL configuration bits */
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390 tmpreg |= RCC_PLLSource | RCC_PLLMul;
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391 /* Store the new value */
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392 RCC->CFGR = tmpreg;
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396 * @brief Enables or disables the PLL.
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397 * @note The PLL can not be disabled if it is used as system clock.
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398 * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
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401 void RCC_PLLCmd(FunctionalState NewState)
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403 /* Check the parameters */
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404 assert_param(IS_FUNCTIONAL_STATE(NewState));
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406 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
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409 #ifdef STM32F10X_CL
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411 * @brief Configures the PREDIV1 division factor.
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413 * - This function must be used only when the PLL is disabled.
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414 * - This function applies only to STM32 Connectivity line devices.
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415 * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
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416 * This parameter can be one of the following values:
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417 * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
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418 * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
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419 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
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420 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
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423 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
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425 uint32_t tmpreg = 0;
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427 /* Check the parameters */
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428 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
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429 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
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431 tmpreg = RCC->CFGR2;
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432 /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
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433 tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
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434 /* Set the PREDIV1 clock source and division factor */
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435 tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
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436 /* Store the new value */
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437 RCC->CFGR2 = tmpreg;
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442 * @brief Configures the PREDIV2 division factor.
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444 * - This function must be used only when both PLL2 and PLL3 are disabled.
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445 * - This function applies only to STM32 Connectivity line devices.
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446 * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
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447 * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
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450 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
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452 uint32_t tmpreg = 0;
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454 /* Check the parameters */
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455 assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
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457 tmpreg = RCC->CFGR2;
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458 /* Clear PREDIV2[3:0] bits */
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459 tmpreg &= ~CFGR2_PREDIV2;
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460 /* Set the PREDIV2 division factor */
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461 tmpreg |= RCC_PREDIV2_Div;
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462 /* Store the new value */
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463 RCC->CFGR2 = tmpreg;
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467 * @brief Configures the PLL2 multiplication factor.
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469 * - This function must be used only when the PLL2 is disabled.
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470 * - This function applies only to STM32 Connectivity line devices.
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471 * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
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472 * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
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475 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
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477 uint32_t tmpreg = 0;
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479 /* Check the parameters */
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480 assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
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482 tmpreg = RCC->CFGR2;
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483 /* Clear PLL2Mul[3:0] bits */
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484 tmpreg &= ~CFGR2_PLL2MUL;
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485 /* Set the PLL2 configuration bits */
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486 tmpreg |= RCC_PLL2Mul;
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487 /* Store the new value */
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488 RCC->CFGR2 = tmpreg;
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493 * @brief Enables or disables the PLL2.
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495 * - The PLL2 can not be disabled if it is used indirectly as system clock
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496 * (i.e. it is used as PLL clock entry that is used as System clock).
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497 * - This function applies only to STM32 Connectivity line devices.
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498 * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
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501 void RCC_PLL2Cmd(FunctionalState NewState)
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503 /* Check the parameters */
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504 assert_param(IS_FUNCTIONAL_STATE(NewState));
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506 *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
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511 * @brief Configures the PLL3 multiplication factor.
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513 * - This function must be used only when the PLL3 is disabled.
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514 * - This function applies only to STM32 Connectivity line devices.
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515 * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
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516 * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
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519 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
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521 uint32_t tmpreg = 0;
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523 /* Check the parameters */
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524 assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
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526 tmpreg = RCC->CFGR2;
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527 /* Clear PLL3Mul[3:0] bits */
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528 tmpreg &= ~CFGR2_PLL3MUL;
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529 /* Set the PLL3 configuration bits */
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530 tmpreg |= RCC_PLL3Mul;
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531 /* Store the new value */
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532 RCC->CFGR2 = tmpreg;
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537 * @brief Enables or disables the PLL3.
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538 * @note This function applies only to STM32 Connectivity line devices.
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539 * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
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542 void RCC_PLL3Cmd(FunctionalState NewState)
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544 /* Check the parameters */
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546 assert_param(IS_FUNCTIONAL_STATE(NewState));
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547 *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
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549 #endif /* STM32F10X_CL */
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552 * @brief Configures the system clock (SYSCLK).
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553 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
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554 * This parameter can be one of the following values:
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555 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
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556 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
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557 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
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560 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
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562 uint32_t tmpreg = 0;
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563 /* Check the parameters */
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564 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
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565 tmpreg = RCC->CFGR;
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566 /* Clear SW[1:0] bits */
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567 tmpreg &= CFGR_SW_Mask;
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568 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
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569 tmpreg |= RCC_SYSCLKSource;
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570 /* Store the new value */
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571 RCC->CFGR = tmpreg;
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575 * @brief Returns the clock source used as system clock.
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577 * @retval The clock source used as system clock. The returned value can
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578 * be one of the following:
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579 * - 0x00: HSI used as system clock
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580 * - 0x04: HSE used as system clock
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581 * - 0x08: PLL used as system clock
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583 uint8_t RCC_GetSYSCLKSource(void)
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585 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
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589 * @brief Configures the AHB clock (HCLK).
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590 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
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591 * the system clock (SYSCLK).
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592 * This parameter can be one of the following values:
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593 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
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594 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
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595 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
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596 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
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597 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
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598 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
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599 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
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600 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
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601 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
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604 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
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606 uint32_t tmpreg = 0;
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607 /* Check the parameters */
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608 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
\r
609 tmpreg = RCC->CFGR;
\r
610 /* Clear HPRE[3:0] bits */
\r
611 tmpreg &= CFGR_HPRE_Reset_Mask;
\r
612 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
\r
613 tmpreg |= RCC_SYSCLK;
\r
614 /* Store the new value */
\r
615 RCC->CFGR = tmpreg;
\r
619 * @brief Configures the Low Speed APB clock (PCLK1).
\r
620 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
\r
621 * the AHB clock (HCLK).
\r
622 * This parameter can be one of the following values:
\r
623 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
\r
624 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
\r
625 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
\r
626 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
\r
627 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
\r
630 void RCC_PCLK1Config(uint32_t RCC_HCLK)
\r
632 uint32_t tmpreg = 0;
\r
633 /* Check the parameters */
\r
634 assert_param(IS_RCC_PCLK(RCC_HCLK));
\r
635 tmpreg = RCC->CFGR;
\r
636 /* Clear PPRE1[2:0] bits */
\r
637 tmpreg &= CFGR_PPRE1_Reset_Mask;
\r
638 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
\r
639 tmpreg |= RCC_HCLK;
\r
640 /* Store the new value */
\r
641 RCC->CFGR = tmpreg;
\r
645 * @brief Configures the High Speed APB clock (PCLK2).
\r
646 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
\r
647 * the AHB clock (HCLK).
\r
648 * This parameter can be one of the following values:
\r
649 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
\r
650 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
\r
651 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
\r
652 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
\r
653 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
\r
656 void RCC_PCLK2Config(uint32_t RCC_HCLK)
\r
658 uint32_t tmpreg = 0;
\r
659 /* Check the parameters */
\r
660 assert_param(IS_RCC_PCLK(RCC_HCLK));
\r
661 tmpreg = RCC->CFGR;
\r
662 /* Clear PPRE2[2:0] bits */
\r
663 tmpreg &= CFGR_PPRE2_Reset_Mask;
\r
664 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
\r
665 tmpreg |= RCC_HCLK << 3;
\r
666 /* Store the new value */
\r
667 RCC->CFGR = tmpreg;
\r
671 * @brief Enables or disables the specified RCC interrupts.
\r
672 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
\r
674 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
\r
675 * of the following values
\r
676 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
677 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
678 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
679 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
680 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
681 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
682 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
684 * For @b other_STM32_devices, this parameter can be any combination of the
\r
685 * following values
\r
686 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
687 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
688 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
689 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
690 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
692 * @param NewState: new state of the specified RCC interrupts.
\r
693 * This parameter can be: ENABLE or DISABLE.
\r
696 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
\r
698 /* Check the parameters */
\r
699 assert_param(IS_RCC_IT(RCC_IT));
\r
700 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
701 if (NewState != DISABLE)
\r
703 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
\r
704 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
\r
708 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
\r
709 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
\r
713 #ifndef STM32F10X_CL
\r
715 * @brief Configures the USB clock (USBCLK).
\r
716 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
\r
717 * derived from the PLL output.
\r
718 * This parameter can be one of the following values:
\r
719 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
\r
721 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
\r
724 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
\r
726 /* Check the parameters */
\r
727 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
\r
729 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
\r
733 * @brief Configures the USB OTG FS clock (OTGFSCLK).
\r
734 * This function applies only to STM32 Connectivity line devices.
\r
735 * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
\r
736 * This clock is derived from the PLL output.
\r
737 * This parameter can be one of the following values:
\r
738 * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
\r
739 * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
\r
742 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
\r
744 /* Check the parameters */
\r
745 assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
\r
747 *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
\r
749 #endif /* STM32F10X_CL */
\r
752 * @brief Configures the ADC clock (ADCCLK).
\r
753 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
\r
754 * the APB2 clock (PCLK2).
\r
755 * This parameter can be one of the following values:
\r
756 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
\r
757 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
\r
758 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
\r
759 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
\r
762 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
\r
764 uint32_t tmpreg = 0;
\r
765 /* Check the parameters */
\r
766 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
\r
767 tmpreg = RCC->CFGR;
\r
768 /* Clear ADCPRE[1:0] bits */
\r
769 tmpreg &= CFGR_ADCPRE_Reset_Mask;
\r
770 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
\r
771 tmpreg |= RCC_PCLK2;
\r
772 /* Store the new value */
\r
773 RCC->CFGR = tmpreg;
\r
776 #ifdef STM32F10X_CL
\r
778 * @brief Configures the I2S2 clock source(I2S2CLK).
\r
780 * - This function must be called before enabling I2S2 APB clock.
\r
781 * - This function applies only to STM32 Connectivity line devices.
\r
782 * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
\r
783 * This parameter can be one of the following values:
\r
784 * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
\r
785 * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
\r
788 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
\r
790 /* Check the parameters */
\r
791 assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
\r
793 *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
\r
797 * @brief Configures the I2S3 clock source(I2S2CLK).
\r
799 * - This function must be called before enabling I2S3 APB clock.
\r
800 * - This function applies only to STM32 Connectivity line devices.
\r
801 * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
\r
802 * This parameter can be one of the following values:
\r
803 * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
\r
804 * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
\r
807 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
\r
809 /* Check the parameters */
\r
810 assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
\r
812 *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
\r
814 #endif /* STM32F10X_CL */
\r
817 * @brief Configures the External Low Speed oscillator (LSE).
\r
818 * @param RCC_LSE: specifies the new state of the LSE.
\r
819 * This parameter can be one of the following values:
\r
820 * @arg RCC_LSE_OFF: LSE oscillator OFF
\r
821 * @arg RCC_LSE_ON: LSE oscillator ON
\r
822 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
\r
825 void RCC_LSEConfig(uint8_t RCC_LSE)
\r
827 /* Check the parameters */
\r
828 assert_param(IS_RCC_LSE(RCC_LSE));
\r
829 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
\r
830 /* Reset LSEON bit */
\r
831 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
\r
832 /* Reset LSEBYP bit */
\r
833 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
\r
834 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
\r
838 /* Set LSEON bit */
\r
839 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
\r
842 case RCC_LSE_Bypass:
\r
843 /* Set LSEBYP and LSEON bits */
\r
844 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
\r
853 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
\r
854 * @note LSI can not be disabled if the IWDG is running.
\r
855 * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
\r
858 void RCC_LSICmd(FunctionalState NewState)
\r
860 /* Check the parameters */
\r
861 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
862 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
\r
866 * @brief Configures the RTC clock (RTCCLK).
\r
867 * @note Once the RTC clock is selected it can
\92t be changed unless the Backup domain is reset.
\r
868 * @param RCC_RTCCLKSource: specifies the RTC clock source.
\r
869 * This parameter can be one of the following values:
\r
870 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
\r
871 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
\r
872 * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
\r
875 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
\r
877 /* Check the parameters */
\r
878 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
\r
879 /* Select the RTC clock source */
\r
880 RCC->BDCR |= RCC_RTCCLKSource;
\r
884 * @brief Enables or disables the RTC clock.
\r
885 * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
\r
886 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
\r
889 void RCC_RTCCLKCmd(FunctionalState NewState)
\r
891 /* Check the parameters */
\r
892 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
893 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
\r
897 * @brief Returns the frequencies of different on chip clocks.
\r
898 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
\r
899 * the clocks frequencies.
\r
902 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
\r
904 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
\r
906 #ifdef STM32F10X_CL
\r
907 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
\r
908 #endif /* STM32F10X_CL */
\r
910 /* Get SYSCLK source -------------------------------------------------------*/
\r
911 tmp = RCC->CFGR & CFGR_SWS_Mask;
\r
915 case 0x00: /* HSI used as system clock */
\r
916 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
918 case 0x04: /* HSE used as system clock */
\r
919 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
\r
921 case 0x08: /* PLL used as system clock */
\r
923 /* Get PLL clock source and multiplication factor ----------------------*/
\r
924 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
\r
925 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
\r
927 #ifndef STM32F10X_CL
\r
928 pllmull = ( pllmull >> 18) + 2;
\r
930 if (pllsource == 0x00)
\r
931 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
\r
932 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\r
935 {/* HSE selected as PLL clock entry */
\r
936 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
\r
937 {/* HSE oscillator clock divided by 2 */
\r
938 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
\r
942 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
\r
946 pllmull = pllmull >> 18;
\r
948 if (pllmull != 0x0D)
\r
953 { /* PLL multiplication factor = PLL input clock * 6.5 */
\r
957 if (pllsource == 0x00)
\r
958 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
\r
959 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
\r
962 {/* PREDIV1 selected as PLL clock entry */
\r
964 /* Get PREDIV1 clock source and division factor */
\r
965 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
\r
966 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
\r
968 if (prediv1source == 0)
\r
969 { /* HSE oscillator clock selected as PREDIV1 clock entry */
\r
970 RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
\r
973 {/* PLL2 clock selected as PREDIV1 clock entry */
\r
975 /* Get PREDIV2 division factor and PLL2 multiplication factor */
\r
976 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
\r
977 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
\r
978 RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
\r
981 #endif /* STM32F10X_CL */
\r
985 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
\r
989 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
\r
990 /* Get HCLK prescaler */
\r
991 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
\r
993 presc = APBAHBPrescTable[tmp];
\r
994 /* HCLK clock frequency */
\r
995 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
\r
996 /* Get PCLK1 prescaler */
\r
997 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
\r
999 presc = APBAHBPrescTable[tmp];
\r
1000 /* PCLK1 clock frequency */
\r
1001 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
1002 /* Get PCLK2 prescaler */
\r
1003 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
\r
1005 presc = APBAHBPrescTable[tmp];
\r
1006 /* PCLK2 clock frequency */
\r
1007 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
\r
1008 /* Get ADCCLK prescaler */
\r
1009 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
\r
1011 presc = ADCPrescTable[tmp];
\r
1012 /* ADCCLK clock frequency */
\r
1013 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
\r
1017 * @brief Enables or disables the AHB peripheral clock.
\r
1018 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
\r
1020 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
\r
1021 * of the following values:
\r
1022 * @arg RCC_AHBPeriph_DMA1
\r
1023 * @arg RCC_AHBPeriph_DMA2
\r
1024 * @arg RCC_AHBPeriph_SRAM
\r
1025 * @arg RCC_AHBPeriph_FLITF
\r
1026 * @arg RCC_AHBPeriph_CRC
\r
1027 * @arg RCC_AHBPeriph_OTG_FS
\r
1028 * @arg RCC_AHBPeriph_ETH_MAC
\r
1029 * @arg RCC_AHBPeriph_ETH_MAC_Tx
\r
1030 * @arg RCC_AHBPeriph_ETH_MAC_Rx
\r
1032 * For @b other_STM32_devices, this parameter can be any combination of the
\r
1033 * following values:
\r
1034 * @arg RCC_AHBPeriph_DMA1
\r
1035 * @arg RCC_AHBPeriph_DMA2
\r
1036 * @arg RCC_AHBPeriph_SRAM
\r
1037 * @arg RCC_AHBPeriph_FLITF
\r
1038 * @arg RCC_AHBPeriph_CRC
\r
1039 * @arg RCC_AHBPeriph_FSMC
\r
1040 * @arg RCC_AHBPeriph_SDIO
\r
1042 * @note SRAM and FLITF clock can be disabled only during sleep mode.
\r
1043 * @param NewState: new state of the specified peripheral clock.
\r
1044 * This parameter can be: ENABLE or DISABLE.
\r
1047 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
\r
1049 /* Check the parameters */
\r
1050 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
\r
1051 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1053 if (NewState != DISABLE)
\r
1055 RCC->AHBENR |= RCC_AHBPeriph;
\r
1059 RCC->AHBENR &= ~RCC_AHBPeriph;
\r
1064 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
\r
1065 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
\r
1066 * This parameter can be any combination of the following values:
\r
1067 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
\r
1068 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
\r
1069 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
\r
1070 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
\r
1071 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
\r
1072 * @param NewState: new state of the specified peripheral clock.
\r
1073 * This parameter can be: ENABLE or DISABLE.
\r
1076 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
\r
1078 /* Check the parameters */
\r
1079 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
1080 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1081 if (NewState != DISABLE)
\r
1083 RCC->APB2ENR |= RCC_APB2Periph;
\r
1087 RCC->APB2ENR &= ~RCC_APB2Periph;
\r
1092 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
\r
1093 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
\r
1094 * This parameter can be any combination of the following values:
\r
1095 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
\r
1096 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
\r
1097 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
\r
1098 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
\r
1099 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
\r
1100 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
\r
1101 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
\r
1102 * @param NewState: new state of the specified peripheral clock.
\r
1103 * This parameter can be: ENABLE or DISABLE.
\r
1106 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
\r
1108 /* Check the parameters */
\r
1109 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
1110 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1111 if (NewState != DISABLE)
\r
1113 RCC->APB1ENR |= RCC_APB1Periph;
\r
1117 RCC->APB1ENR &= ~RCC_APB1Periph;
\r
1121 #ifdef STM32F10X_CL
\r
1123 * @brief Forces or releases AHB peripheral reset.
\r
1124 * @note This function applies only to STM32 Connectivity line devices.
\r
1125 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
\r
1126 * This parameter can be any combination of the following values:
\r
1127 * @arg RCC_AHBPeriph_OTG_FS
\r
1128 * @arg RCC_AHBPeriph_ETH_MAC
\r
1129 * @param NewState: new state of the specified peripheral reset.
\r
1130 * This parameter can be: ENABLE or DISABLE.
\r
1133 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
\r
1135 /* Check the parameters */
\r
1136 assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
\r
1137 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1139 if (NewState != DISABLE)
\r
1141 RCC->AHBRSTR |= RCC_AHBPeriph;
\r
1145 RCC->AHBRSTR &= ~RCC_AHBPeriph;
\r
1148 #endif /* STM32F10X_CL */
\r
1151 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
\r
1152 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
\r
1153 * This parameter can be any combination of the following values:
\r
1154 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
\r
1155 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
\r
1156 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
\r
1157 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
\r
1158 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
\r
1159 * @param NewState: new state of the specified peripheral reset.
\r
1160 * This parameter can be: ENABLE or DISABLE.
\r
1163 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
\r
1165 /* Check the parameters */
\r
1166 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
\r
1167 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1168 if (NewState != DISABLE)
\r
1170 RCC->APB2RSTR |= RCC_APB2Periph;
\r
1174 RCC->APB2RSTR &= ~RCC_APB2Periph;
\r
1179 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
\r
1180 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
\r
1181 * This parameter can be any combination of the following values:
\r
1182 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
\r
1183 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
\r
1184 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
\r
1185 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
\r
1186 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
\r
1187 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
\r
1188 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
\r
1189 * @param NewState: new state of the specified peripheral clock.
\r
1190 * This parameter can be: ENABLE or DISABLE.
\r
1193 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
\r
1195 /* Check the parameters */
\r
1196 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
\r
1197 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1198 if (NewState != DISABLE)
\r
1200 RCC->APB1RSTR |= RCC_APB1Periph;
\r
1204 RCC->APB1RSTR &= ~RCC_APB1Periph;
\r
1209 * @brief Forces or releases the Backup domain reset.
\r
1210 * @param NewState: new state of the Backup domain reset.
\r
1211 * This parameter can be: ENABLE or DISABLE.
\r
1214 void RCC_BackupResetCmd(FunctionalState NewState)
\r
1216 /* Check the parameters */
\r
1217 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1218 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
\r
1222 * @brief Enables or disables the Clock Security System.
\r
1223 * @param NewState: new state of the Clock Security System..
\r
1224 * This parameter can be: ENABLE or DISABLE.
\r
1227 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
\r
1229 /* Check the parameters */
\r
1230 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1231 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
\r
1235 * @brief Selects the clock source to output on MCO pin.
\r
1236 * @param RCC_MCO: specifies the clock source to output.
\r
1238 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
\r
1239 * following values:
\r
1240 * @arg RCC_MCO_NoClock: No clock selected
\r
1241 * @arg RCC_MCO_SYSCLK: System clock selected
\r
1242 * @arg RCC_MCO_HSI: HSI oscillator clock selected
\r
1243 * @arg RCC_MCO_HSE: HSE oscillator clock selected
\r
1244 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
\r
1245 * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
\r
1246 * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
\r
1247 * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
\r
1248 * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
\r
1250 * For @b other_STM32_devices, this parameter can be one of the following values:
\r
1251 * @arg RCC_MCO_NoClock: No clock selected
\r
1252 * @arg RCC_MCO_SYSCLK: System clock selected
\r
1253 * @arg RCC_MCO_HSI: HSI oscillator clock selected
\r
1254 * @arg RCC_MCO_HSE: HSE oscillator clock selected
\r
1255 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
\r
1259 void RCC_MCOConfig(uint8_t RCC_MCO)
\r
1261 /* Check the parameters */
\r
1262 assert_param(IS_RCC_MCO(RCC_MCO));
\r
1264 /* Perform Byte access to MCO bits to select the MCO source */
\r
1265 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
\r
1269 * @brief Checks whether the specified RCC flag is set or not.
\r
1270 * @param RCC_FLAG: specifies the flag to check.
\r
1272 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
\r
1273 * following values:
\r
1274 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
1275 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
1276 * @arg RCC_FLAG_PLLRDY: PLL clock ready
\r
1277 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
\r
1278 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
\r
1279 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
1280 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
1281 * @arg RCC_FLAG_PINRST: Pin reset
\r
1282 * @arg RCC_FLAG_PORRST: POR/PDR reset
\r
1283 * @arg RCC_FLAG_SFTRST: Software reset
\r
1284 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
\r
1285 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
\r
1286 * @arg RCC_FLAG_LPWRRST: Low Power reset
\r
1288 * For @b other_STM32_devices, this parameter can be one of the following values:
\r
1289 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
\r
1290 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
\r
1291 * @arg RCC_FLAG_PLLRDY: PLL clock ready
\r
1292 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
\r
1293 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
\r
1294 * @arg RCC_FLAG_PINRST: Pin reset
\r
1295 * @arg RCC_FLAG_PORRST: POR/PDR reset
\r
1296 * @arg RCC_FLAG_SFTRST: Software reset
\r
1297 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
\r
1298 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
\r
1299 * @arg RCC_FLAG_LPWRRST: Low Power reset
\r
1301 * @retval The new state of RCC_FLAG (SET or RESET).
\r
1303 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
\r
1306 uint32_t statusreg = 0;
\r
1307 FlagStatus bitstatus = RESET;
\r
1308 /* Check the parameters */
\r
1309 assert_param(IS_RCC_FLAG(RCC_FLAG));
\r
1311 /* Get the RCC register index */
\r
1312 tmp = RCC_FLAG >> 5;
\r
1313 if (tmp == 1) /* The flag to check is in CR register */
\r
1315 statusreg = RCC->CR;
\r
1317 else if (tmp == 2) /* The flag to check is in BDCR register */
\r
1319 statusreg = RCC->BDCR;
\r
1321 else /* The flag to check is in CSR register */
\r
1323 statusreg = RCC->CSR;
\r
1326 /* Get the flag position */
\r
1327 tmp = RCC_FLAG & FLAG_Mask;
\r
1328 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
\r
1334 bitstatus = RESET;
\r
1337 /* Return the flag status */
\r
1342 * @brief Clears the RCC reset flags.
\r
1343 * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
\r
1344 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
\r
1348 void RCC_ClearFlag(void)
\r
1350 /* Set RMVF bit to clear the reset flags */
\r
1351 RCC->CSR |= CSR_RMVF_Set;
\r
1355 * @brief Checks whether the specified RCC interrupt has occurred or not.
\r
1356 * @param RCC_IT: specifies the RCC interrupt source to check.
\r
1358 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
\r
1359 * following values:
\r
1360 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1361 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1362 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1363 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1364 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1365 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
1366 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
1367 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1369 * For @b other_STM32_devices, this parameter can be one of the following values:
\r
1370 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1371 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1372 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1373 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1374 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1375 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1377 * @retval The new state of RCC_IT (SET or RESET).
\r
1379 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
\r
1381 ITStatus bitstatus = RESET;
\r
1382 /* Check the parameters */
\r
1383 assert_param(IS_RCC_GET_IT(RCC_IT));
\r
1385 /* Check the status of the specified RCC interrupt */
\r
1386 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
\r
1392 bitstatus = RESET;
\r
1395 /* Return the RCC_IT status */
\r
1400 * @brief Clears the RCC
\92s interrupt pending bits.
\r
1401 * @param RCC_IT: specifies the interrupt pending bit to clear.
\r
1403 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
\r
1404 * of the following values:
\r
1405 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1406 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1407 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1408 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1409 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1410 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
\r
1411 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
\r
1412 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1414 * For @b other_STM32_devices, this parameter can be any combination of the
\r
1415 * following values:
\r
1416 * @arg RCC_IT_LSIRDY: LSI ready interrupt
\r
1417 * @arg RCC_IT_LSERDY: LSE ready interrupt
\r
1418 * @arg RCC_IT_HSIRDY: HSI ready interrupt
\r
1419 * @arg RCC_IT_HSERDY: HSE ready interrupt
\r
1420 * @arg RCC_IT_PLLRDY: PLL ready interrupt
\r
1422 * @arg RCC_IT_CSS: Clock Security System interrupt
\r
1425 void RCC_ClearITPendingBit(uint8_t RCC_IT)
\r
1427 /* Check the parameters */
\r
1428 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
\r
1430 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
\r
1432 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
\r
1447 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
\r