2 ******************************************************************************
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3 * @file stm32f10x_tim.c
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4 * @author MCD Application Team
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7 * @brief This file provides all the TIM firmware functions.
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8 ******************************************************************************
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11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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21 /* Includes ------------------------------------------------------------------*/
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22 #include "stm32f10x_tim.h"
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23 #include "stm32f10x_rcc.h"
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25 /** @addtogroup STM32F10x_StdPeriph_Driver
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30 * @brief TIM driver modules
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34 /** @defgroup TIM_Private_TypesDefinitions
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42 /** @defgroup TIM_Private_Defines
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46 /* ---------------------- TIM registers bit mask ------------------------ */
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47 #define CR1_CEN_Set ((uint16_t)0x0001)
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48 #define CR1_CEN_Reset ((uint16_t)0x03FE)
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49 #define CR1_UDIS_Set ((uint16_t)0x0002)
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50 #define CR1_UDIS_Reset ((uint16_t)0x03FD)
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51 #define CR1_URS_Set ((uint16_t)0x0004)
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52 #define CR1_URS_Reset ((uint16_t)0x03FB)
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53 #define CR1_OPM_Reset ((uint16_t)0x03F7)
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54 #define CR1_CounterMode_Mask ((uint16_t)0x038F)
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55 #define CR1_ARPE_Set ((uint16_t)0x0080)
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56 #define CR1_ARPE_Reset ((uint16_t)0x037F)
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57 #define CR1_CKD_Mask ((uint16_t)0x00FF)
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58 #define CR2_CCPC_Set ((uint16_t)0x0001)
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59 #define CR2_CCPC_Reset ((uint16_t)0xFFFE)
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60 #define CR2_CCUS_Set ((uint16_t)0x0004)
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61 #define CR2_CCUS_Reset ((uint16_t)0xFFFB)
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62 #define CR2_CCDS_Set ((uint16_t)0x0008)
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63 #define CR2_CCDS_Reset ((uint16_t)0xFFF7)
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64 #define CR2_MMS_Mask ((uint16_t)0xFF8F)
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65 #define CR2_TI1S_Set ((uint16_t)0x0080)
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66 #define CR2_TI1S_Reset ((uint16_t)0xFF7F)
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67 #define CR2_OIS1_Reset ((uint16_t)0x7EFF)
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68 #define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
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69 #define CR2_OIS2_Reset ((uint16_t)0x7BFF)
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70 #define CR2_OIS2N_Reset ((uint16_t)0x77FF)
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71 #define CR2_OIS3_Reset ((uint16_t)0x6FFF)
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72 #define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
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73 #define CR2_OIS4_Reset ((uint16_t)0x3FFF)
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74 #define SMCR_SMS_Mask ((uint16_t)0xFFF8)
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75 #define SMCR_ETR_Mask ((uint16_t)0x00FF)
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76 #define SMCR_TS_Mask ((uint16_t)0xFF8F)
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77 #define SMCR_MSM_Reset ((uint16_t)0xFF7F)
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78 #define SMCR_ECE_Set ((uint16_t)0x4000)
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79 #define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
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80 #define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
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81 #define CCMR_TI13Direct_Set ((uint16_t)0x0001)
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82 #define CCMR_TI24Direct_Set ((uint16_t)0x0100)
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83 #define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
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84 #define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
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85 #define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
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86 #define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
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87 #define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
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88 #define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
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89 #define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
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90 #define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
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91 #define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
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92 #define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
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93 #define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
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94 #define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
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95 #define CCMR_Offset ((uint16_t)0x0018)
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96 #define CCER_CCE_Set ((uint16_t)0x0001)
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97 #define CCER_CCNE_Set ((uint16_t)0x0004)
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98 #define CCER_CC1P_Reset ((uint16_t)0xFFFD)
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99 #define CCER_CC2P_Reset ((uint16_t)0xFFDF)
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100 #define CCER_CC3P_Reset ((uint16_t)0xFDFF)
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101 #define CCER_CC4P_Reset ((uint16_t)0xDFFF)
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102 #define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
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103 #define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
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104 #define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
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105 #define CCER_CC1E_Set ((uint16_t)0x0001)
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106 #define CCER_CC1E_Reset ((uint16_t)0xFFFE)
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107 #define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
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108 #define CCER_CC2E_Set ((uint16_t)0x0010)
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109 #define CCER_CC2E_Reset ((uint16_t)0xFFEF)
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110 #define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
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111 #define CCER_CC3E_Set ((uint16_t)0x0100)
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112 #define CCER_CC3E_Reset ((uint16_t)0xFEFF)
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113 #define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
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114 #define CCER_CC4E_Set ((uint16_t)0x1000)
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115 #define CCER_CC4E_Reset ((uint16_t)0xEFFF)
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116 #define BDTR_MOE_Set ((uint16_t)0x8000)
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117 #define BDTR_MOE_Reset ((uint16_t)0x7FFF)
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122 /** @defgroup TIM_Private_Macros
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130 /** @defgroup TIM_Private_Variables
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138 /** @defgroup TIM_Private_FunctionPrototypes
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142 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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143 uint16_t TIM_ICFilter);
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144 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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145 uint16_t TIM_ICFilter);
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146 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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147 uint16_t TIM_ICFilter);
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148 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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149 uint16_t TIM_ICFilter);
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154 /** @defgroup TIM_Private_Macros
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162 /** @defgroup TIM_Private_Variables
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170 /** @defgroup TIM_Private_FunctionPrototypes
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178 /** @defgroup TIM_Private_Functions
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183 * @brief Deinitializes the TIMx peripheral registers to their default reset values.
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184 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
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187 void TIM_DeInit(TIM_TypeDef* TIMx)
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189 /* Check the parameters */
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190 assert_param(IS_TIM_ALL_PERIPH(TIMx));
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194 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
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195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
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197 else if (TIMx == TIM2)
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199 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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200 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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202 else if (TIMx == TIM3)
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204 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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205 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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207 else if (TIMx == TIM4)
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209 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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210 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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212 else if (TIMx == TIM5)
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214 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
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215 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
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217 else if (TIMx == TIM6)
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219 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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220 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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222 else if (TIMx == TIM7)
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224 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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225 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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231 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
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232 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
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238 * @brief Initializes the TIMx Time Base Unit peripheral according to
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239 * the specified parameters in the TIM_TimeBaseInitStruct.
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240 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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241 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
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242 * structure that contains the configuration information for the specified TIM peripheral.
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245 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
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247 /* Check the parameters */
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248 assert_param(IS_TIM_123458_PERIPH(TIMx));
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249 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
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250 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
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251 /* Select the Counter Mode and set the clock division */
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252 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
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253 TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
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254 TIM_TimeBaseInitStruct->TIM_CounterMode;
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256 /* Set the Autoreload value */
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257 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
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259 /* Set the Prescaler value */
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260 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
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262 if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE))
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264 /* Set the Repetition Counter value */
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265 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
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268 /* Generate an update event to reload the Prescaler value immediatly */
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269 TIMx->EGR = TIM_PSCReloadMode_Immediate;
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273 * @brief Initializes the TIMx Channel1 according to the specified
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274 * parameters in the TIM_OCInitStruct.
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275 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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276 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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277 * that contains the configuration information for the specified TIM peripheral.
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280 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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282 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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284 /* Check the parameters */
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285 assert_param(IS_TIM_123458_PERIPH(TIMx));
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286 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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287 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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288 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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289 /* Disable the Channel 1: Reset the CC1E Bit */
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290 TIMx->CCER &= CCER_CC1E_Reset;
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292 /* Get the TIMx CCER register value */
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293 tmpccer = TIMx->CCER;
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294 /* Get the TIMx CR2 register value */
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295 tmpcr2 = TIMx->CR2;
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297 /* Get the TIMx CCMR1 register value */
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298 tmpccmrx = TIMx->CCMR1;
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300 /* Reset the Output Compare mode and Capture/Compare selection Bits */
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301 tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
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303 /* Select the Output Compare Mode */
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304 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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306 /* Reset the Output Polarity level */
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307 tmpccer &= CCER_CC1P_Reset;
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308 /* Set the Output Compare Polarity */
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309 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
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311 /* Set the Output State */
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312 tmpccer |= TIM_OCInitStruct->TIM_OutputState;
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314 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
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316 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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317 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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318 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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319 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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321 /* Reset the Output N Polarity level */
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322 tmpccer &= CCER_CC1NP_Reset;
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323 /* Set the Output N Polarity */
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324 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
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325 /* Reset the Output N State */
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326 tmpccer &= CCER_CC1NE_Reset;
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328 /* Set the Output N State */
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329 tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
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330 /* Reset the Ouput Compare and Output Compare N IDLE State */
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331 tmpcr2 &= CR2_OIS1_Reset;
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332 tmpcr2 &= CR2_OIS1N_Reset;
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333 /* Set the Output Idle state */
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334 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
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335 /* Set the Output N Idle state */
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336 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
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338 /* Write to TIMx CR2 */
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339 TIMx->CR2 = tmpcr2;
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341 /* Write to TIMx CCMR1 */
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342 TIMx->CCMR1 = tmpccmrx;
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344 /* Set the Capture Compare Register value */
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345 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
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347 /* Write to TIMx CCER */
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348 TIMx->CCER = tmpccer;
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352 * @brief Initializes the TIMx Channel2 according to the specified
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353 * parameters in the TIM_OCInitStruct.
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354 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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355 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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356 * that contains the configuration information for the specified TIM peripheral.
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359 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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361 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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363 /* Check the parameters */
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364 assert_param(IS_TIM_123458_PERIPH(TIMx));
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365 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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366 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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367 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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368 /* Disable the Channel 2: Reset the CC2E Bit */
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369 TIMx->CCER &= CCER_CC2E_Reset;
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371 /* Get the TIMx CCER register value */
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372 tmpccer = TIMx->CCER;
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373 /* Get the TIMx CR2 register value */
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374 tmpcr2 = TIMx->CR2;
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376 /* Get the TIMx CCMR1 register value */
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377 tmpccmrx = TIMx->CCMR1;
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379 /* Reset the Output Compare mode and Capture/Compare selection Bits */
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380 tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
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382 /* Select the Output Compare Mode */
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383 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
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385 /* Reset the Output Polarity level */
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386 tmpccer &= CCER_CC2P_Reset;
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387 /* Set the Output Compare Polarity */
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388 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
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390 /* Set the Output State */
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391 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
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393 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
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395 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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396 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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397 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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398 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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400 /* Reset the Output N Polarity level */
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401 tmpccer &= CCER_CC2NP_Reset;
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402 /* Set the Output N Polarity */
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403 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
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404 /* Reset the Output N State */
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405 tmpccer &= CCER_CC2NE_Reset;
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407 /* Set the Output N State */
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408 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
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409 /* Reset the Ouput Compare and Output Compare N IDLE State */
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410 tmpcr2 &= CR2_OIS2_Reset;
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411 tmpcr2 &= CR2_OIS2N_Reset;
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412 /* Set the Output Idle state */
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413 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
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414 /* Set the Output N Idle state */
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415 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
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417 /* Write to TIMx CR2 */
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418 TIMx->CR2 = tmpcr2;
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420 /* Write to TIMx CCMR1 */
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421 TIMx->CCMR1 = tmpccmrx;
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423 /* Set the Capture Compare Register value */
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424 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
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426 /* Write to TIMx CCER */
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427 TIMx->CCER = tmpccer;
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431 * @brief Initializes the TIMx Channel3 according to the specified
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432 * parameters in the TIM_OCInitStruct.
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433 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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434 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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435 * that contains the configuration information for the specified TIM peripheral.
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438 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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440 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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442 /* Check the parameters */
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443 assert_param(IS_TIM_123458_PERIPH(TIMx));
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444 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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445 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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446 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
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447 /* Disable the Channel 2: Reset the CC2E Bit */
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448 TIMx->CCER &= CCER_CC3E_Reset;
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450 /* Get the TIMx CCER register value */
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451 tmpccer = TIMx->CCER;
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452 /* Get the TIMx CR2 register value */
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453 tmpcr2 = TIMx->CR2;
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455 /* Get the TIMx CCMR2 register value */
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456 tmpccmrx = TIMx->CCMR2;
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458 /* Reset the Output Compare mode and Capture/Compare selection Bits */
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459 tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
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461 /* Select the Output Compare Mode */
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462 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
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464 /* Reset the Output Polarity level */
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465 tmpccer &= CCER_CC3P_Reset;
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466 /* Set the Output Compare Polarity */
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467 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
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469 /* Set the Output State */
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470 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
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472 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
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474 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
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475 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
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476 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
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477 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
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479 /* Reset the Output N Polarity level */
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480 tmpccer &= CCER_CC3NP_Reset;
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481 /* Set the Output N Polarity */
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482 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
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483 /* Reset the Output N State */
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484 tmpccer &= CCER_CC3NE_Reset;
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486 /* Set the Output N State */
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487 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
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488 /* Reset the Ouput Compare and Output Compare N IDLE State */
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489 tmpcr2 &= CR2_OIS3_Reset;
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490 tmpcr2 &= CR2_OIS3N_Reset;
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491 /* Set the Output Idle state */
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492 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
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493 /* Set the Output N Idle state */
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494 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
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496 /* Write to TIMx CR2 */
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497 TIMx->CR2 = tmpcr2;
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499 /* Write to TIMx CCMR2 */
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500 TIMx->CCMR2 = tmpccmrx;
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502 /* Set the Capture Compare Register value */
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503 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
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505 /* Write to TIMx CCER */
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506 TIMx->CCER = tmpccer;
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510 * @brief Initializes the TIMx Channel4 according to the specified
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511 * parameters in the TIM_OCInitStruct.
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512 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
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513 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
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514 * that contains the configuration information for the specified TIM peripheral.
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517 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
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519 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
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521 /* Check the parameters */
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522 assert_param(IS_TIM_123458_PERIPH(TIMx));
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523 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
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524 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
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525 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
\r
526 /* Disable the Channel 2: Reset the CC4E Bit */
\r
527 TIMx->CCER &= CCER_CC4E_Reset;
\r
529 /* Get the TIMx CCER register value */
\r
530 tmpccer = TIMx->CCER;
\r
531 /* Get the TIMx CR2 register value */
\r
532 tmpcr2 = TIMx->CR2;
\r
534 /* Get the TIMx CCMR2 register value */
\r
535 tmpccmrx = TIMx->CCMR2;
\r
537 /* Reset the Output Compare mode and Capture/Compare selection Bits */
\r
538 tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
\r
540 /* Select the Output Compare Mode */
\r
541 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
\r
543 /* Reset the Output Polarity level */
\r
544 tmpccer &= CCER_CC4P_Reset;
\r
545 /* Set the Output Compare Polarity */
\r
546 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
\r
548 /* Set the Output State */
\r
549 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
\r
551 if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
\r
553 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
\r
554 /* Reset the Ouput Compare IDLE State */
\r
555 tmpcr2 &= CR2_OIS4_Reset;
\r
556 /* Set the Output Idle state */
\r
557 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
\r
559 /* Write to TIMx CR2 */
\r
560 TIMx->CR2 = tmpcr2;
\r
562 /* Write to TIMx CCMR2 */
\r
563 TIMx->CCMR2 = tmpccmrx;
\r
565 /* Set the Capture Compare Register value */
\r
566 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
\r
568 /* Write to TIMx CCER */
\r
569 TIMx->CCER = tmpccer;
\r
573 * @brief Initializes the TIM peripheral according to the specified
\r
574 * parameters in the TIM_ICInitStruct.
\r
575 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
576 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
577 * that contains the configuration information for the specified TIM peripheral.
\r
580 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
582 /* Check the parameters */
\r
583 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
584 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
\r
585 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
\r
586 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
\r
587 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
\r
588 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
\r
590 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
592 /* TI1 Configuration */
\r
593 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
594 TIM_ICInitStruct->TIM_ICSelection,
\r
595 TIM_ICInitStruct->TIM_ICFilter);
\r
596 /* Set the Input Capture Prescaler value */
\r
597 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
599 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
\r
601 /* TI2 Configuration */
\r
602 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
603 TIM_ICInitStruct->TIM_ICSelection,
\r
604 TIM_ICInitStruct->TIM_ICFilter);
\r
605 /* Set the Input Capture Prescaler value */
\r
606 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
608 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
\r
610 /* TI3 Configuration */
\r
611 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
612 TIM_ICInitStruct->TIM_ICSelection,
\r
613 TIM_ICInitStruct->TIM_ICFilter);
\r
614 /* Set the Input Capture Prescaler value */
\r
615 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
619 /* TI4 Configuration */
\r
620 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
\r
621 TIM_ICInitStruct->TIM_ICSelection,
\r
622 TIM_ICInitStruct->TIM_ICFilter);
\r
623 /* Set the Input Capture Prescaler value */
\r
624 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
629 * @brief Configures the TIM peripheral according to the specified
\r
630 * parameters in the TIM_ICInitStruct to measure an external PWM signal.
\r
631 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
632 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
\r
633 * that contains the configuration information for the specified TIM peripheral.
\r
636 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
638 uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
\r
639 uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
\r
640 /* Check the parameters */
\r
641 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
642 /* Select the Opposite Input Polarity */
\r
643 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
\r
645 icoppositepolarity = TIM_ICPolarity_Falling;
\r
649 icoppositepolarity = TIM_ICPolarity_Rising;
\r
651 /* Select the Opposite Input */
\r
652 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
\r
654 icoppositeselection = TIM_ICSelection_IndirectTI;
\r
658 icoppositeselection = TIM_ICSelection_DirectTI;
\r
660 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
\r
662 /* TI1 Configuration */
\r
663 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
664 TIM_ICInitStruct->TIM_ICFilter);
\r
665 /* Set the Input Capture Prescaler value */
\r
666 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
667 /* TI2 Configuration */
\r
668 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
669 /* Set the Input Capture Prescaler value */
\r
670 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
674 /* TI2 Configuration */
\r
675 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
\r
676 TIM_ICInitStruct->TIM_ICFilter);
\r
677 /* Set the Input Capture Prescaler value */
\r
678 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
679 /* TI1 Configuration */
\r
680 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
\r
681 /* Set the Input Capture Prescaler value */
\r
682 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
\r
687 * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
\r
688 * the OSSR State and the AOE(automatic output enable).
\r
689 * @param TIMx: where x can be 1 or 8 to select the TIM
\r
690 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
\r
691 * contains the BDTR Register configuration information for the TIM peripheral.
\r
694 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
\r
696 /* Check the parameters */
\r
697 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
698 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
\r
699 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
\r
700 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
\r
701 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
\r
702 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
\r
703 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
\r
704 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
\r
705 the OSSI State, the dead time value and the Automatic Output Enable Bit */
\r
706 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
\r
707 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
\r
708 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
\r
709 TIM_BDTRInitStruct->TIM_AutomaticOutput;
\r
713 * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
\r
714 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
\r
715 * structure which will be initialized.
\r
718 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
\r
720 /* Set the default configuration */
\r
721 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
\r
722 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
\r
723 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
\r
724 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
\r
725 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
\r
729 * @brief Fills each TIM_OCInitStruct member with its default value.
\r
730 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
\r
734 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
\r
736 /* Set the default configuration */
\r
737 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
\r
738 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
\r
739 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
\r
740 TIM_OCInitStruct->TIM_Pulse = 0x0000;
\r
741 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
\r
742 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
\r
743 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
\r
744 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
\r
748 * @brief Fills each TIM_ICInitStruct member with its default value.
\r
749 * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
\r
753 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
\r
755 /* Set the default configuration */
\r
756 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
\r
757 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
\r
758 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
\r
759 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
\r
760 TIM_ICInitStruct->TIM_ICFilter = 0x00;
\r
764 * @brief Fills each TIM_BDTRInitStruct member with its default value.
\r
765 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
\r
766 * will be initialized.
\r
769 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
\r
771 /* Set the default configuration */
\r
772 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
\r
773 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
\r
774 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
\r
775 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
\r
776 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
\r
777 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
\r
778 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
\r
782 * @brief Enables or disables the specified TIM peripheral.
\r
783 * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
\r
784 * @param NewState: new state of the TIMx peripheral.
\r
785 * This parameter can be: ENABLE or DISABLE.
\r
788 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
790 /* Check the parameters */
\r
791 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
792 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
794 if (NewState != DISABLE)
\r
796 /* Enable the TIM Counter */
\r
797 TIMx->CR1 |= CR1_CEN_Set;
\r
801 /* Disable the TIM Counter */
\r
802 TIMx->CR1 &= CR1_CEN_Reset;
\r
807 * @brief Enables or disables the TIM peripheral Main Outputs.
\r
808 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
\r
809 * @param NewState: new state of the TIM peripheral Main Outputs.
\r
810 * This parameter can be: ENABLE or DISABLE.
\r
813 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
815 /* Check the parameters */
\r
816 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
817 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
818 if (NewState != DISABLE)
\r
820 /* Enable the TIM Main Output */
\r
821 TIMx->BDTR |= BDTR_MOE_Set;
\r
825 /* Disable the TIM Main Output */
\r
826 TIMx->BDTR &= BDTR_MOE_Reset;
\r
831 * @brief Enables or disables the specified TIM interrupts.
\r
832 * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
\r
833 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
\r
834 * This parameter can be any combination of the following values:
\r
835 * @arg TIM_IT_Update: TIM update Interrupt source
\r
836 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
837 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
838 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
839 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
840 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
841 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
842 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
844 * - TIM6 and TIM7 can only generate an update interrupt.
\r
845 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
\r
846 * @param NewState: new state of the TIM interrupts.
\r
847 * This parameter can be: ENABLE or DISABLE.
\r
850 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
\r
852 /* Check the parameters */
\r
853 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
854 assert_param(IS_TIM_IT(TIM_IT));
\r
855 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
857 if (NewState != DISABLE)
\r
859 /* Enable the Interrupt sources */
\r
860 TIMx->DIER |= TIM_IT;
\r
864 /* Disable the Interrupt sources */
\r
865 TIMx->DIER &= (uint16_t)~TIM_IT;
\r
870 * @brief Configures the TIMx event to be generate by software.
\r
871 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
872 * @param TIM_EventSource: specifies the event source.
\r
873 * This parameter can be one or more of the following values:
\r
874 * @arg TIM_EventSource_Update: Timer update Event source
\r
875 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
\r
876 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
\r
877 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
\r
878 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
\r
879 * @arg TIM_EventSource_COM: Timer COM event source
\r
880 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
\r
881 * @arg TIM_EventSource_Break: Timer Break event source
\r
883 * - TIM6 and TIM7 can only generate an update event.
\r
884 * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
\r
887 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
\r
889 /* Check the parameters */
\r
890 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
891 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
\r
893 /* Set the event sources */
\r
894 TIMx->EGR = TIM_EventSource;
\r
898 * @brief Configures the TIMx
\92s DMA interface.
\r
899 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
900 * @param TIM_DMABase: DMA Base address.
\r
901 * This parameter can be one of the following values:
\r
902 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
\r
903 * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
\r
904 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
\r
905 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
\r
906 * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
\r
907 * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
\r
909 * @param TIM_DMABurstLength: DMA Burst length.
\r
910 * This parameter can be one value between:
\r
911 * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
\r
914 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
\r
916 /* Check the parameters */
\r
917 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
918 assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
\r
919 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
\r
920 /* Set the DMA Base and the DMA Burst Length */
\r
921 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
\r
925 * @brief Enables or disables the TIMx
\92s DMA Requests.
\r
926 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
927 * @param TIM_DMASource: specifies the DMA Request sources.
\r
928 * This parameter can be any combination of the following values:
\r
929 * @arg TIM_DMA_Update: TIM update Interrupt source
\r
930 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
\r
931 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
\r
932 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
\r
933 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
\r
934 * @arg TIM_DMA_COM: TIM Commutation DMA source
\r
935 * @arg TIM_DMA_Trigger: TIM Trigger DMA source
\r
936 * @param NewState: new state of the DMA Request sources.
\r
937 * This parameter can be: ENABLE or DISABLE.
\r
940 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
\r
942 /* Check the parameters */
\r
943 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
944 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
\r
945 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
947 if (NewState != DISABLE)
\r
949 /* Enable the DMA sources */
\r
950 TIMx->DIER |= TIM_DMASource;
\r
954 /* Disable the DMA sources */
\r
955 TIMx->DIER &= (uint16_t)~TIM_DMASource;
\r
960 * @brief Configures the TIMx interrnal Clock
\r
961 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
964 void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
\r
966 /* Check the parameters */
\r
967 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
968 /* Disable slave mode to clock the prescaler directly with the internal clock */
\r
969 TIMx->SMCR &= SMCR_SMS_Mask;
\r
973 * @brief Configures the TIMx Internal Trigger as External Clock
\r
974 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
975 * @param TIM_ITRSource: Trigger source.
\r
976 * This parameter can be one of the following values:
\r
977 * @param TIM_TS_ITR0: Internal Trigger 0
\r
978 * @param TIM_TS_ITR1: Internal Trigger 1
\r
979 * @param TIM_TS_ITR2: Internal Trigger 2
\r
980 * @param TIM_TS_ITR3: Internal Trigger 3
\r
983 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
985 /* Check the parameters */
\r
986 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
987 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
988 /* Select the Internal Trigger */
\r
989 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
\r
990 /* Select the External clock mode1 */
\r
991 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
995 * @brief Configures the TIMx Trigger as External Clock
\r
996 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
997 * @param TIM_TIxExternalCLKSource: Trigger source.
\r
998 * This parameter can be one of the following values:
\r
999 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
\r
1000 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
\r
1001 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
\r
1002 * @param TIM_ICPolarity: specifies the TIx Polarity.
\r
1003 * This parameter can be one of the following values:
\r
1004 * @arg TIM_ICPolarity_Rising
\r
1005 * @arg TIM_ICPolarity_Falling
\r
1006 * @param ICFilter : specifies the filter value.
\r
1007 * This parameter must be a value between 0x0 and 0xF.
\r
1010 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
\r
1011 uint16_t TIM_ICPolarity, uint16_t ICFilter)
\r
1013 /* Check the parameters */
\r
1014 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1015 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
\r
1016 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
\r
1017 assert_param(IS_TIM_IC_FILTER(ICFilter));
\r
1018 /* Configure the Timer Input Clock Source */
\r
1019 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
\r
1021 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
1025 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
\r
1027 /* Select the Trigger source */
\r
1028 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
\r
1029 /* Select the External clock mode1 */
\r
1030 TIMx->SMCR |= TIM_SlaveMode_External1;
\r
1034 * @brief Configures the External clock Mode1
\r
1035 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1036 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1037 * This parameter can be one of the following values:
\r
1038 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1039 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1040 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1041 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1042 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1043 * This parameter can be one of the following values:
\r
1044 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1045 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1046 * @param ExtTRGFilter: External Trigger Filter.
\r
1047 * This parameter must be a value between 0x00 and 0x0F
\r
1050 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
1051 uint16_t ExtTRGFilter)
\r
1053 uint16_t tmpsmcr = 0;
\r
1054 /* Check the parameters */
\r
1055 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1056 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1057 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1058 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1059 /* Configure the ETR Clock source */
\r
1060 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
1062 /* Get the TIMx SMCR register value */
\r
1063 tmpsmcr = TIMx->SMCR;
\r
1064 /* Reset the SMS Bits */
\r
1065 tmpsmcr &= SMCR_SMS_Mask;
\r
1066 /* Select the External clock mode1 */
\r
1067 tmpsmcr |= TIM_SlaveMode_External1;
\r
1068 /* Select the Trigger selection : ETRF */
\r
1069 tmpsmcr &= SMCR_TS_Mask;
\r
1070 tmpsmcr |= TIM_TS_ETRF;
\r
1071 /* Write to TIMx SMCR */
\r
1072 TIMx->SMCR = tmpsmcr;
\r
1076 * @brief Configures the External clock Mode2
\r
1077 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1078 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1079 * This parameter can be one of the following values:
\r
1080 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1081 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1082 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1083 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1084 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1085 * This parameter can be one of the following values:
\r
1086 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1087 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1088 * @param ExtTRGFilter: External Trigger Filter.
\r
1089 * This parameter must be a value between 0x00 and 0x0F
\r
1092 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
\r
1093 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
\r
1095 /* Check the parameters */
\r
1096 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1097 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1098 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1099 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1100 /* Configure the ETR Clock source */
\r
1101 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
\r
1102 /* Enable the External clock mode2 */
\r
1103 TIMx->SMCR |= SMCR_ECE_Set;
\r
1107 * @brief Configures the TIMx External Trigger (ETR).
\r
1108 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1109 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
\r
1110 * This parameter can be one of the following values:
\r
1111 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
\r
1112 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
\r
1113 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
\r
1114 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
\r
1115 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
\r
1116 * This parameter can be one of the following values:
\r
1117 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
\r
1118 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
\r
1119 * @param ExtTRGFilter: External Trigger Filter.
\r
1120 * This parameter must be a value between 0x00 and 0x0F
\r
1123 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
\r
1124 uint16_t ExtTRGFilter)
\r
1126 uint16_t tmpsmcr = 0;
\r
1127 /* Check the parameters */
\r
1128 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1129 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
\r
1130 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
\r
1131 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
\r
1132 tmpsmcr = TIMx->SMCR;
\r
1133 /* Reset the ETR Bits */
\r
1134 tmpsmcr &= SMCR_ETR_Mask;
\r
1135 /* Set the Prescaler, the Filter value and the Polarity */
\r
1136 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
\r
1137 /* Write to TIMx SMCR */
\r
1138 TIMx->SMCR = tmpsmcr;
\r
1142 * @brief Configures the TIMx Prescaler.
\r
1143 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
1144 * @param Prescaler: specifies the Prescaler Register value
\r
1145 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
\r
1146 * This parameter can be one of the following values:
\r
1147 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
\r
1148 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
\r
1151 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
\r
1153 /* Check the parameters */
\r
1154 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1155 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
\r
1156 /* Set the Prescaler value */
\r
1157 TIMx->PSC = Prescaler;
\r
1158 /* Set or reset the UG Bit */
\r
1159 TIMx->EGR = TIM_PSCReloadMode;
\r
1163 * @brief Specifies the TIMx Counter Mode to be used.
\r
1164 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1165 * @param TIM_CounterMode: specifies the Counter Mode to be used
\r
1166 * This parameter can be one of the following values:
\r
1167 * @arg TIM_CounterMode_Up: TIM Up Counting Mode
\r
1168 * @arg TIM_CounterMode_Down: TIM Down Counting Mode
\r
1169 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
\r
1170 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
\r
1171 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
\r
1174 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
\r
1176 uint16_t tmpcr1 = 0;
\r
1177 /* Check the parameters */
\r
1178 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1179 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
\r
1180 tmpcr1 = TIMx->CR1;
\r
1181 /* Reset the CMS and DIR Bits */
\r
1182 tmpcr1 &= CR1_CounterMode_Mask;
\r
1183 /* Set the Counter Mode */
\r
1184 tmpcr1 |= TIM_CounterMode;
\r
1185 /* Write to TIMx CR1 register */
\r
1186 TIMx->CR1 = tmpcr1;
\r
1190 * @brief Selects the Input Trigger source
\r
1191 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1192 * @param TIM_InputTriggerSource: The Input Trigger source.
\r
1193 * This parameter can be one of the following values:
\r
1194 * @arg TIM_TS_ITR0: Internal Trigger 0
\r
1195 * @arg TIM_TS_ITR1: Internal Trigger 1
\r
1196 * @arg TIM_TS_ITR2: Internal Trigger 2
\r
1197 * @arg TIM_TS_ITR3: Internal Trigger 3
\r
1198 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
\r
1199 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
\r
1200 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
\r
1201 * @arg TIM_TS_ETRF: External Trigger input
\r
1204 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
\r
1206 uint16_t tmpsmcr = 0;
\r
1207 /* Check the parameters */
\r
1208 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1209 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
\r
1210 /* Get the TIMx SMCR register value */
\r
1211 tmpsmcr = TIMx->SMCR;
\r
1212 /* Reset the TS Bits */
\r
1213 tmpsmcr &= SMCR_TS_Mask;
\r
1214 /* Set the Input Trigger source */
\r
1215 tmpsmcr |= TIM_InputTriggerSource;
\r
1216 /* Write to TIMx SMCR */
\r
1217 TIMx->SMCR = tmpsmcr;
\r
1221 * @brief Configures the TIMx Encoder Interface.
\r
1222 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1223 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
\r
1224 * This parameter can be one of the following values:
\r
1225 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
\r
1226 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
\r
1227 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
\r
1228 * on the level of the other input.
\r
1229 * @param TIM_IC1Polarity: specifies the IC1 Polarity
\r
1230 * This parmeter can be one of the following values:
\r
1231 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1232 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1233 * @param TIM_IC2Polarity: specifies the IC2 Polarity
\r
1234 * This parmeter can be one of the following values:
\r
1235 * @arg TIM_ICPolarity_Falling: IC Falling edge.
\r
1236 * @arg TIM_ICPolarity_Rising: IC Rising edge.
\r
1239 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
\r
1240 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
\r
1242 uint16_t tmpsmcr = 0;
\r
1243 uint16_t tmpccmr1 = 0;
\r
1244 uint16_t tmpccer = 0;
\r
1246 /* Check the parameters */
\r
1247 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1248 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
\r
1249 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
\r
1250 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
\r
1252 /* Get the TIMx SMCR register value */
\r
1253 tmpsmcr = TIMx->SMCR;
\r
1255 /* Get the TIMx CCMR1 register value */
\r
1256 tmpccmr1 = TIMx->CCMR1;
\r
1258 /* Get the TIMx CCER register value */
\r
1259 tmpccer = TIMx->CCER;
\r
1261 /* Set the encoder Mode */
\r
1262 tmpsmcr &= SMCR_SMS_Mask;
\r
1263 tmpsmcr |= TIM_EncoderMode;
\r
1265 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
\r
1266 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
\r
1267 tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
\r
1269 /* Set the TI1 and the TI2 Polarities */
\r
1270 tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
\r
1271 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
\r
1273 /* Write to TIMx SMCR */
\r
1274 TIMx->SMCR = tmpsmcr;
\r
1276 /* Write to TIMx CCMR1 */
\r
1277 TIMx->CCMR1 = tmpccmr1;
\r
1279 /* Write to TIMx CCER */
\r
1280 TIMx->CCER = tmpccer;
\r
1284 * @brief Forces the TIMx output 1 waveform to active or inactive level.
\r
1285 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1286 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1287 * This parameter can be one of the following values:
\r
1288 * @arg TIM_ForcedAction_Active: Force active level on OC1REF
\r
1289 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
\r
1292 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1294 uint16_t tmpccmr1 = 0;
\r
1295 /* Check the parameters */
\r
1296 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1297 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1298 tmpccmr1 = TIMx->CCMR1;
\r
1299 /* Reset the OC1M Bits */
\r
1300 tmpccmr1 &= CCMR_OC13M_Mask;
\r
1301 /* Configure The Forced output Mode */
\r
1302 tmpccmr1 |= TIM_ForcedAction;
\r
1303 /* Write to TIMx CCMR1 register */
\r
1304 TIMx->CCMR1 = tmpccmr1;
\r
1308 * @brief Forces the TIMx output 2 waveform to active or inactive level.
\r
1309 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1310 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1311 * This parameter can be one of the following values:
\r
1312 * @arg TIM_ForcedAction_Active: Force active level on OC2REF
\r
1313 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
\r
1316 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1318 uint16_t tmpccmr1 = 0;
\r
1319 /* Check the parameters */
\r
1320 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1321 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1322 tmpccmr1 = TIMx->CCMR1;
\r
1323 /* Reset the OC2M Bits */
\r
1324 tmpccmr1 &= CCMR_OC24M_Mask;
\r
1325 /* Configure The Forced output Mode */
\r
1326 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1327 /* Write to TIMx CCMR1 register */
\r
1328 TIMx->CCMR1 = tmpccmr1;
\r
1332 * @brief Forces the TIMx output 3 waveform to active or inactive level.
\r
1333 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1334 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1335 * This parameter can be one of the following values:
\r
1336 * @arg TIM_ForcedAction_Active: Force active level on OC3REF
\r
1337 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
\r
1340 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1342 uint16_t tmpccmr2 = 0;
\r
1343 /* Check the parameters */
\r
1344 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1345 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1346 tmpccmr2 = TIMx->CCMR2;
\r
1347 /* Reset the OC1M Bits */
\r
1348 tmpccmr2 &= CCMR_OC13M_Mask;
\r
1349 /* Configure The Forced output Mode */
\r
1350 tmpccmr2 |= TIM_ForcedAction;
\r
1351 /* Write to TIMx CCMR2 register */
\r
1352 TIMx->CCMR2 = tmpccmr2;
\r
1356 * @brief Forces the TIMx output 4 waveform to active or inactive level.
\r
1357 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1358 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
\r
1359 * This parameter can be one of the following values:
\r
1360 * @arg TIM_ForcedAction_Active: Force active level on OC4REF
\r
1361 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
\r
1364 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
\r
1366 uint16_t tmpccmr2 = 0;
\r
1367 /* Check the parameters */
\r
1368 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1369 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
\r
1370 tmpccmr2 = TIMx->CCMR2;
\r
1371 /* Reset the OC2M Bits */
\r
1372 tmpccmr2 &= CCMR_OC24M_Mask;
\r
1373 /* Configure The Forced output Mode */
\r
1374 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
\r
1375 /* Write to TIMx CCMR2 register */
\r
1376 TIMx->CCMR2 = tmpccmr2;
\r
1380 * @brief Enables or disables TIMx peripheral Preload register on ARR.
\r
1381 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1382 * @param NewState: new state of the TIMx peripheral Preload register
\r
1383 * This parameter can be: ENABLE or DISABLE.
\r
1386 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1388 /* Check the parameters */
\r
1389 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
1390 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1391 if (NewState != DISABLE)
\r
1393 /* Set the ARR Preload Bit */
\r
1394 TIMx->CR1 |= CR1_ARPE_Set;
\r
1398 /* Reset the ARR Preload Bit */
\r
1399 TIMx->CR1 &= CR1_ARPE_Reset;
\r
1404 * @brief Selects the TIM peripheral Commutation event.
\r
1405 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
\r
1406 * @param NewState: new state of the Commutation event.
\r
1407 * This parameter can be: ENABLE or DISABLE.
\r
1410 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1412 /* Check the parameters */
\r
1413 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1414 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1415 if (NewState != DISABLE)
\r
1417 /* Set the COM Bit */
\r
1418 TIMx->CR2 |= CR2_CCUS_Set;
\r
1422 /* Reset the COM Bit */
\r
1423 TIMx->CR2 &= CR2_CCUS_Reset;
\r
1428 * @brief Selects the TIMx peripheral Capture Compare DMA source.
\r
1429 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1430 * @param NewState: new state of the Capture Compare DMA source
\r
1431 * This parameter can be: ENABLE or DISABLE.
\r
1434 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1436 /* Check the parameters */
\r
1437 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1438 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1439 if (NewState != DISABLE)
\r
1441 /* Set the CCDS Bit */
\r
1442 TIMx->CR2 |= CR2_CCDS_Set;
\r
1446 /* Reset the CCDS Bit */
\r
1447 TIMx->CR2 &= CR2_CCDS_Reset;
\r
1452 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
\r
1453 * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
\r
1454 * @param NewState: new state of the Capture Compare Preload Control bit
\r
1455 * This parameter can be: ENABLE or DISABLE.
\r
1458 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
1460 /* Check the parameters */
\r
1461 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1462 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1463 if (NewState != DISABLE)
\r
1465 /* Set the CCPC Bit */
\r
1466 TIMx->CR2 |= CR2_CCPC_Set;
\r
1470 /* Reset the CCPC Bit */
\r
1471 TIMx->CR2 &= CR2_CCPC_Reset;
\r
1476 * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
\r
1477 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1478 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1479 * This parameter can be one of the following values:
\r
1480 * @arg TIM_OCPreload_Enable
\r
1481 * @arg TIM_OCPreload_Disable
\r
1484 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1486 uint16_t tmpccmr1 = 0;
\r
1487 /* Check the parameters */
\r
1488 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1489 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1490 tmpccmr1 = TIMx->CCMR1;
\r
1491 /* Reset the OC1PE Bit */
\r
1492 tmpccmr1 &= CCMR_OC13PE_Reset;
\r
1493 /* Enable or Disable the Output Compare Preload feature */
\r
1494 tmpccmr1 |= TIM_OCPreload;
\r
1495 /* Write to TIMx CCMR1 register */
\r
1496 TIMx->CCMR1 = tmpccmr1;
\r
1500 * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
\r
1501 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1502 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1503 * This parameter can be one of the following values:
\r
1504 * @arg TIM_OCPreload_Enable
\r
1505 * @arg TIM_OCPreload_Disable
\r
1508 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1510 uint16_t tmpccmr1 = 0;
\r
1511 /* Check the parameters */
\r
1512 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1513 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1514 tmpccmr1 = TIMx->CCMR1;
\r
1515 /* Reset the OC2PE Bit */
\r
1516 tmpccmr1 &= CCMR_OC24PE_Reset;
\r
1517 /* Enable or Disable the Output Compare Preload feature */
\r
1518 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
\r
1519 /* Write to TIMx CCMR1 register */
\r
1520 TIMx->CCMR1 = tmpccmr1;
\r
1524 * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
\r
1525 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1526 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1527 * This parameter can be one of the following values:
\r
1528 * @arg TIM_OCPreload_Enable
\r
1529 * @arg TIM_OCPreload_Disable
\r
1532 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1534 uint16_t tmpccmr2 = 0;
\r
1535 /* Check the parameters */
\r
1536 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1537 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1538 tmpccmr2 = TIMx->CCMR2;
\r
1539 /* Reset the OC3PE Bit */
\r
1540 tmpccmr2 &= CCMR_OC13PE_Reset;
\r
1541 /* Enable or Disable the Output Compare Preload feature */
\r
1542 tmpccmr2 |= TIM_OCPreload;
\r
1543 /* Write to TIMx CCMR2 register */
\r
1544 TIMx->CCMR2 = tmpccmr2;
\r
1548 * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
\r
1549 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1550 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
\r
1551 * This parameter can be one of the following values:
\r
1552 * @arg TIM_OCPreload_Enable
\r
1553 * @arg TIM_OCPreload_Disable
\r
1556 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
\r
1558 uint16_t tmpccmr2 = 0;
\r
1559 /* Check the parameters */
\r
1560 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1561 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
\r
1562 tmpccmr2 = TIMx->CCMR2;
\r
1563 /* Reset the OC4PE Bit */
\r
1564 tmpccmr2 &= CCMR_OC24PE_Reset;
\r
1565 /* Enable or Disable the Output Compare Preload feature */
\r
1566 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
\r
1567 /* Write to TIMx CCMR2 register */
\r
1568 TIMx->CCMR2 = tmpccmr2;
\r
1572 * @brief Configures the TIMx Output Compare 1 Fast feature.
\r
1573 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1574 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1575 * This parameter can be one of the following values:
\r
1576 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1577 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1580 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1582 uint16_t tmpccmr1 = 0;
\r
1583 /* Check the parameters */
\r
1584 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1585 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1586 /* Get the TIMx CCMR1 register value */
\r
1587 tmpccmr1 = TIMx->CCMR1;
\r
1588 /* Reset the OC1FE Bit */
\r
1589 tmpccmr1 &= CCMR_OC13FE_Reset;
\r
1590 /* Enable or Disable the Output Compare Fast Bit */
\r
1591 tmpccmr1 |= TIM_OCFast;
\r
1592 /* Write to TIMx CCMR1 */
\r
1593 TIMx->CCMR1 = tmpccmr1;
\r
1597 * @brief Configures the TIMx Output Compare 2 Fast feature.
\r
1598 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1599 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1600 * This parameter can be one of the following values:
\r
1601 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1602 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1605 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1607 uint16_t tmpccmr1 = 0;
\r
1608 /* Check the parameters */
\r
1609 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1610 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1611 /* Get the TIMx CCMR1 register value */
\r
1612 tmpccmr1 = TIMx->CCMR1;
\r
1613 /* Reset the OC2FE Bit */
\r
1614 tmpccmr1 &= CCMR_OC24FE_Reset;
\r
1615 /* Enable or Disable the Output Compare Fast Bit */
\r
1616 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
\r
1617 /* Write to TIMx CCMR1 */
\r
1618 TIMx->CCMR1 = tmpccmr1;
\r
1622 * @brief Configures the TIMx Output Compare 3 Fast feature.
\r
1623 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1624 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1625 * This parameter can be one of the following values:
\r
1626 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1627 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1630 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1632 uint16_t tmpccmr2 = 0;
\r
1633 /* Check the parameters */
\r
1634 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1635 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1636 /* Get the TIMx CCMR2 register value */
\r
1637 tmpccmr2 = TIMx->CCMR2;
\r
1638 /* Reset the OC3FE Bit */
\r
1639 tmpccmr2 &= CCMR_OC13FE_Reset;
\r
1640 /* Enable or Disable the Output Compare Fast Bit */
\r
1641 tmpccmr2 |= TIM_OCFast;
\r
1642 /* Write to TIMx CCMR2 */
\r
1643 TIMx->CCMR2 = tmpccmr2;
\r
1647 * @brief Configures the TIMx Output Compare 4 Fast feature.
\r
1648 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1649 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
\r
1650 * This parameter can be one of the following values:
\r
1651 * @arg TIM_OCFast_Enable: TIM output compare fast enable
\r
1652 * @arg TIM_OCFast_Disable: TIM output compare fast disable
\r
1655 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
\r
1657 uint16_t tmpccmr2 = 0;
\r
1658 /* Check the parameters */
\r
1659 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1660 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
\r
1661 /* Get the TIMx CCMR2 register value */
\r
1662 tmpccmr2 = TIMx->CCMR2;
\r
1663 /* Reset the OC4FE Bit */
\r
1664 tmpccmr2 &= CCMR_OC24FE_Reset;
\r
1665 /* Enable or Disable the Output Compare Fast Bit */
\r
1666 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
\r
1667 /* Write to TIMx CCMR2 */
\r
1668 TIMx->CCMR2 = tmpccmr2;
\r
1672 * @brief Clears or safeguards the OCREF1 signal on an external event
\r
1673 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1674 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1675 * This parameter can be one of the following values:
\r
1676 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1677 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1680 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1682 uint16_t tmpccmr1 = 0;
\r
1683 /* Check the parameters */
\r
1684 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1685 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1686 tmpccmr1 = TIMx->CCMR1;
\r
1687 /* Reset the OC1CE Bit */
\r
1688 tmpccmr1 &= CCMR_OC13CE_Reset;
\r
1689 /* Enable or Disable the Output Compare Clear Bit */
\r
1690 tmpccmr1 |= TIM_OCClear;
\r
1691 /* Write to TIMx CCMR1 register */
\r
1692 TIMx->CCMR1 = tmpccmr1;
\r
1696 * @brief Clears or safeguards the OCREF2 signal on an external event
\r
1697 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1698 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1699 * This parameter can be one of the following values:
\r
1700 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1701 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1704 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1706 uint16_t tmpccmr1 = 0;
\r
1707 /* Check the parameters */
\r
1708 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1709 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1710 tmpccmr1 = TIMx->CCMR1;
\r
1711 /* Reset the OC2CE Bit */
\r
1712 tmpccmr1 &= CCMR_OC24CE_Reset;
\r
1713 /* Enable or Disable the Output Compare Clear Bit */
\r
1714 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
\r
1715 /* Write to TIMx CCMR1 register */
\r
1716 TIMx->CCMR1 = tmpccmr1;
\r
1720 * @brief Clears or safeguards the OCREF3 signal on an external event
\r
1721 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1722 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1723 * This parameter can be one of the following values:
\r
1724 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1725 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1728 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1730 uint16_t tmpccmr2 = 0;
\r
1731 /* Check the parameters */
\r
1732 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1733 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1734 tmpccmr2 = TIMx->CCMR2;
\r
1735 /* Reset the OC3CE Bit */
\r
1736 tmpccmr2 &= CCMR_OC13CE_Reset;
\r
1737 /* Enable or Disable the Output Compare Clear Bit */
\r
1738 tmpccmr2 |= TIM_OCClear;
\r
1739 /* Write to TIMx CCMR2 register */
\r
1740 TIMx->CCMR2 = tmpccmr2;
\r
1744 * @brief Clears or safeguards the OCREF4 signal on an external event
\r
1745 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1746 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
\r
1747 * This parameter can be one of the following values:
\r
1748 * @arg TIM_OCClear_Enable: TIM Output clear enable
\r
1749 * @arg TIM_OCClear_Disable: TIM Output clear disable
\r
1752 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
\r
1754 uint16_t tmpccmr2 = 0;
\r
1755 /* Check the parameters */
\r
1756 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1757 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
\r
1758 tmpccmr2 = TIMx->CCMR2;
\r
1759 /* Reset the OC4CE Bit */
\r
1760 tmpccmr2 &= CCMR_OC24CE_Reset;
\r
1761 /* Enable or Disable the Output Compare Clear Bit */
\r
1762 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
\r
1763 /* Write to TIMx CCMR2 register */
\r
1764 TIMx->CCMR2 = tmpccmr2;
\r
1768 * @brief Configures the TIMx channel 1 polarity.
\r
1769 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1770 * @param TIM_OCPolarity: specifies the OC1 Polarity
\r
1771 * This parmeter can be one of the following values:
\r
1772 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1773 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1776 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1778 uint16_t tmpccer = 0;
\r
1779 /* Check the parameters */
\r
1780 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1781 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1782 tmpccer = TIMx->CCER;
\r
1783 /* Set or Reset the CC1P Bit */
\r
1784 tmpccer &= CCER_CC1P_Reset;
\r
1785 tmpccer |= TIM_OCPolarity;
\r
1786 /* Write to TIMx CCER register */
\r
1787 TIMx->CCER = tmpccer;
\r
1791 * @brief Configures the TIMx Channel 1N polarity.
\r
1792 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1793 * @param TIM_OCNPolarity: specifies the OC1N Polarity
\r
1794 * This parmeter can be one of the following values:
\r
1795 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1796 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1799 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1801 uint16_t tmpccer = 0;
\r
1802 /* Check the parameters */
\r
1803 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1804 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1806 tmpccer = TIMx->CCER;
\r
1807 /* Set or Reset the CC1NP Bit */
\r
1808 tmpccer &= CCER_CC1NP_Reset;
\r
1809 tmpccer |= TIM_OCNPolarity;
\r
1810 /* Write to TIMx CCER register */
\r
1811 TIMx->CCER = tmpccer;
\r
1815 * @brief Configures the TIMx channel 2 polarity.
\r
1816 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1817 * @param TIM_OCPolarity: specifies the OC2 Polarity
\r
1818 * This parmeter can be one of the following values:
\r
1819 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1820 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1823 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1825 uint16_t tmpccer = 0;
\r
1826 /* Check the parameters */
\r
1827 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1828 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1829 tmpccer = TIMx->CCER;
\r
1830 /* Set or Reset the CC2P Bit */
\r
1831 tmpccer &= CCER_CC2P_Reset;
\r
1832 tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
\r
1833 /* Write to TIMx CCER register */
\r
1834 TIMx->CCER = tmpccer;
\r
1838 * @brief Configures the TIMx Channel 2N polarity.
\r
1839 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1840 * @param TIM_OCNPolarity: specifies the OC2N Polarity
\r
1841 * This parmeter can be one of the following values:
\r
1842 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1843 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1846 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1848 uint16_t tmpccer = 0;
\r
1849 /* Check the parameters */
\r
1850 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1851 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1853 tmpccer = TIMx->CCER;
\r
1854 /* Set or Reset the CC2NP Bit */
\r
1855 tmpccer &= CCER_CC2NP_Reset;
\r
1856 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
\r
1857 /* Write to TIMx CCER register */
\r
1858 TIMx->CCER = tmpccer;
\r
1862 * @brief Configures the TIMx channel 3 polarity.
\r
1863 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1864 * @param TIM_OCPolarity: specifies the OC3 Polarity
\r
1865 * This parmeter can be one of the following values:
\r
1866 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1867 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1870 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1872 uint16_t tmpccer = 0;
\r
1873 /* Check the parameters */
\r
1874 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1875 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1876 tmpccer = TIMx->CCER;
\r
1877 /* Set or Reset the CC3P Bit */
\r
1878 tmpccer &= CCER_CC3P_Reset;
\r
1879 tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
\r
1880 /* Write to TIMx CCER register */
\r
1881 TIMx->CCER = tmpccer;
\r
1885 * @brief Configures the TIMx Channel 3N polarity.
\r
1886 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1887 * @param TIM_OCNPolarity: specifies the OC3N Polarity
\r
1888 * This parmeter can be one of the following values:
\r
1889 * @arg TIM_OCNPolarity_High: Output Compare active high
\r
1890 * @arg TIM_OCNPolarity_Low: Output Compare active low
\r
1893 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
\r
1895 uint16_t tmpccer = 0;
\r
1897 /* Check the parameters */
\r
1898 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1899 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
\r
1901 tmpccer = TIMx->CCER;
\r
1902 /* Set or Reset the CC3NP Bit */
\r
1903 tmpccer &= CCER_CC3NP_Reset;
\r
1904 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
\r
1905 /* Write to TIMx CCER register */
\r
1906 TIMx->CCER = tmpccer;
\r
1910 * @brief Configures the TIMx channel 4 polarity.
\r
1911 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1912 * @param TIM_OCPolarity: specifies the OC4 Polarity
\r
1913 * This parmeter can be one of the following values:
\r
1914 * @arg TIM_OCPolarity_High: Output Compare active high
\r
1915 * @arg TIM_OCPolarity_Low: Output Compare active low
\r
1918 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
\r
1920 uint16_t tmpccer = 0;
\r
1921 /* Check the parameters */
\r
1922 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1923 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
\r
1924 tmpccer = TIMx->CCER;
\r
1925 /* Set or Reset the CC4P Bit */
\r
1926 tmpccer &= CCER_CC4P_Reset;
\r
1927 tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
\r
1928 /* Write to TIMx CCER register */
\r
1929 TIMx->CCER = tmpccer;
\r
1933 * @brief Enables or disables the TIM Capture Compare Channel x.
\r
1934 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1935 * @param TIM_Channel: specifies the TIM Channel
\r
1936 * This parmeter can be one of the following values:
\r
1937 * @arg TIM_Channel_1: TIM Channel 1
\r
1938 * @arg TIM_Channel_2: TIM Channel 2
\r
1939 * @arg TIM_Channel_3: TIM Channel 3
\r
1940 * @arg TIM_Channel_4: TIM Channel 4
\r
1941 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
\r
1942 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
\r
1945 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
\r
1949 /* Check the parameters */
\r
1950 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
1951 assert_param(IS_TIM_CHANNEL(TIM_Channel));
\r
1952 assert_param(IS_TIM_CCX(TIM_CCx));
\r
1954 tmp = CCER_CCE_Set << TIM_Channel;
\r
1956 /* Reset the CCxE Bit */
\r
1957 TIMx->CCER &= (uint16_t)~ tmp;
\r
1959 /* Set or reset the CCxE Bit */
\r
1960 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
\r
1964 * @brief Enables or disables the TIM Capture Compare Channel xN.
\r
1965 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
\r
1966 * @param TIM_Channel: specifies the TIM Channel
\r
1967 * This parmeter can be one of the following values:
\r
1968 * @arg TIM_Channel_1: TIM Channel 1
\r
1969 * @arg TIM_Channel_2: TIM Channel 2
\r
1970 * @arg TIM_Channel_3: TIM Channel 3
\r
1971 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
\r
1972 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
\r
1975 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
\r
1979 /* Check the parameters */
\r
1980 assert_param(IS_TIM_18_PERIPH(TIMx));
\r
1981 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
\r
1982 assert_param(IS_TIM_CCXN(TIM_CCxN));
\r
1984 tmp = CCER_CCNE_Set << TIM_Channel;
\r
1986 /* Reset the CCxNE Bit */
\r
1987 TIMx->CCER &= (uint16_t) ~tmp;
\r
1989 /* Set or reset the CCxNE Bit */
\r
1990 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
\r
1994 * @brief Selects the TIM Ouput Compare Mode.
\r
1995 * @note This function disables the selected channel before changing the Ouput
\r
1997 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
\r
1998 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
1999 * @param TIM_Channel: specifies the TIM Channel
\r
2000 * This parmeter can be one of the following values:
\r
2001 * @arg TIM_Channel_1: TIM Channel 1
\r
2002 * @arg TIM_Channel_2: TIM Channel 2
\r
2003 * @arg TIM_Channel_3: TIM Channel 3
\r
2004 * @arg TIM_Channel_4: TIM Channel 4
\r
2005 * @param TIM_OCMode: specifies the TIM Output Compare Mode.
\r
2006 * This paramter can be one of the following values:
\r
2007 * @arg TIM_OCMode_Timing
\r
2008 * @arg TIM_OCMode_Active
\r
2009 * @arg TIM_OCMode_Toggle
\r
2010 * @arg TIM_OCMode_PWM1
\r
2011 * @arg TIM_OCMode_PWM2
\r
2012 * @arg TIM_ForcedAction_Active
\r
2013 * @arg TIM_ForcedAction_InActive
\r
2016 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
\r
2019 uint16_t tmp1 = 0;
\r
2021 /* Check the parameters */
\r
2022 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2023 assert_param(IS_TIM_CHANNEL(TIM_Channel));
\r
2024 assert_param(IS_TIM_OCM(TIM_OCMode));
\r
2026 tmp = (uint32_t) TIMx;
\r
2027 tmp += CCMR_Offset;
\r
2029 tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
\r
2031 /* Disable the Channel: Reset the CCxE Bit */
\r
2032 TIMx->CCER &= (uint16_t) ~tmp1;
\r
2034 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
\r
2036 tmp += (TIM_Channel>>1);
\r
2038 /* Reset the OCxM bits in the CCMRx register */
\r
2039 *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask;
\r
2041 /* Configure the OCxM bits in the CCMRx register */
\r
2042 *(__IO uint32_t *) tmp |= TIM_OCMode;
\r
2046 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
\r
2048 /* Reset the OCxM bits in the CCMRx register */
\r
2049 *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask;
\r
2051 /* Configure the OCxM bits in the CCMRx register */
\r
2052 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
\r
2057 * @brief Enables or Disables the TIMx Update event.
\r
2058 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2059 * @param NewState: new state of the TIMx UDIS bit
\r
2060 * This parameter can be: ENABLE or DISABLE.
\r
2063 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2065 /* Check the parameters */
\r
2066 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2067 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2068 if (NewState != DISABLE)
\r
2070 /* Set the Update Disable Bit */
\r
2071 TIMx->CR1 |= CR1_UDIS_Set;
\r
2075 /* Reset the Update Disable Bit */
\r
2076 TIMx->CR1 &= CR1_UDIS_Reset;
\r
2081 * @brief Configures the TIMx Update Request Interrupt source.
\r
2082 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2083 * @param TIM_UpdateSource: specifies the Update source.
\r
2084 * This parameter can be one of the following values:
\r
2085 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
\r
2086 or the setting of UG bit, or an update generation
\r
2087 through the slave mode controller.
\r
2088 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
\r
2091 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
\r
2093 /* Check the parameters */
\r
2094 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2095 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
\r
2096 if (TIM_UpdateSource != TIM_UpdateSource_Global)
\r
2098 /* Set the URS Bit */
\r
2099 TIMx->CR1 |= CR1_URS_Set;
\r
2103 /* Reset the URS Bit */
\r
2104 TIMx->CR1 &= CR1_URS_Reset;
\r
2109 * @brief Enables or disables the TIMx
\92s Hall sensor interface.
\r
2110 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2111 * @param NewState: new state of the TIMx Hall sensor interface.
\r
2112 * This parameter can be: ENABLE or DISABLE.
\r
2115 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
\r
2117 /* Check the parameters */
\r
2118 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2119 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
2120 if (NewState != DISABLE)
\r
2122 /* Set the TI1S Bit */
\r
2123 TIMx->CR2 |= CR2_TI1S_Set;
\r
2127 /* Reset the TI1S Bit */
\r
2128 TIMx->CR2 &= CR2_TI1S_Reset;
\r
2133 * @brief Selects the TIMx
\92s One Pulse Mode.
\r
2134 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2135 * @param TIM_OPMode: specifies the OPM Mode to be used.
\r
2136 * This parameter can be one of the following values:
\r
2137 * @arg TIM_OPMode_Single
\r
2138 * @arg TIM_OPMode_Repetitive
\r
2141 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
\r
2143 /* Check the parameters */
\r
2144 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2145 assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
\r
2146 /* Reset the OPM Bit */
\r
2147 TIMx->CR1 &= CR1_OPM_Reset;
\r
2148 /* Configure the OPM Mode */
\r
2149 TIMx->CR1 |= TIM_OPMode;
\r
2153 * @brief Selects the TIMx Trigger Output Mode.
\r
2154 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2155 * @param TIM_TRGOSource: specifies the Trigger Output source.
\r
2156 * This paramter can be one of the following values:
\r
2159 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
\r
2160 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
\r
2161 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
\r
2163 * - For all TIMx except TIM6 and TIM7
\r
2164 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
\r
2165 * is to be set, as soon as a capture or compare match occurs (TRGO).
\r
2166 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
\r
2167 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
\r
2168 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
\r
2169 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
\r
2173 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
\r
2175 /* Check the parameters */
\r
2176 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2177 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
\r
2178 /* Reset the MMS Bits */
\r
2179 TIMx->CR2 &= CR2_MMS_Mask;
\r
2180 /* Select the TRGO source */
\r
2181 TIMx->CR2 |= TIM_TRGOSource;
\r
2185 * @brief Selects the TIMx Slave Mode.
\r
2186 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2187 * @param TIM_SlaveMode: specifies the Timer Slave Mode.
\r
2188 * This paramter can be one of the following values:
\r
2189 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
\r
2190 * the counter and triggers an update of the registers.
\r
2191 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
\r
2192 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
\r
2193 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
\r
2196 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
\r
2198 /* Check the parameters */
\r
2199 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2200 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
\r
2201 /* Reset the SMS Bits */
\r
2202 TIMx->SMCR &= SMCR_SMS_Mask;
\r
2203 /* Select the Slave Mode */
\r
2204 TIMx->SMCR |= TIM_SlaveMode;
\r
2208 * @brief Sets or Resets the TIMx Master/Slave Mode.
\r
2209 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2210 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
\r
2211 * This paramter can be one of the following values:
\r
2212 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
\r
2213 * and its slaves (through TRGO).
\r
2214 * @arg TIM_MasterSlaveMode_Disable: No action
\r
2217 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
\r
2219 /* Check the parameters */
\r
2220 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2221 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
\r
2222 /* Reset the MSM Bit */
\r
2223 TIMx->SMCR &= SMCR_MSM_Reset;
\r
2225 /* Set or Reset the MSM Bit */
\r
2226 TIMx->SMCR |= TIM_MasterSlaveMode;
\r
2230 * @brief Sets the TIMx Counter Register value
\r
2231 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2232 * @param Counter: specifies the Counter register new value.
\r
2235 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
\r
2237 /* Check the parameters */
\r
2238 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2239 /* Set the Counter Register value */
\r
2240 TIMx->CNT = Counter;
\r
2244 * @brief Sets the TIMx Autoreload Register value
\r
2245 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2246 * @param Autoreload: specifies the Autoreload register new value.
\r
2249 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
\r
2251 /* Check the parameters */
\r
2252 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2253 /* Set the Autoreload Register value */
\r
2254 TIMx->ARR = Autoreload;
\r
2258 * @brief Sets the TIMx Capture Compare1 Register value
\r
2259 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2260 * @param Compare1: specifies the Capture Compare1 register new value.
\r
2263 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
\r
2265 /* Check the parameters */
\r
2266 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2267 /* Set the Capture Compare1 Register value */
\r
2268 TIMx->CCR1 = Compare1;
\r
2272 * @brief Sets the TIMx Capture Compare2 Register value
\r
2273 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2274 * @param Compare2: specifies the Capture Compare2 register new value.
\r
2277 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
\r
2279 /* Check the parameters */
\r
2280 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2281 /* Set the Capture Compare2 Register value */
\r
2282 TIMx->CCR2 = Compare2;
\r
2286 * @brief Sets the TIMx Capture Compare3 Register value
\r
2287 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2288 * @param Compare3: specifies the Capture Compare3 register new value.
\r
2291 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
\r
2293 /* Check the parameters */
\r
2294 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2295 /* Set the Capture Compare3 Register value */
\r
2296 TIMx->CCR3 = Compare3;
\r
2300 * @brief Sets the TIMx Capture Compare4 Register value
\r
2301 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2302 * @param Compare4: specifies the Capture Compare4 register new value.
\r
2305 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
\r
2307 /* Check the parameters */
\r
2308 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2309 /* Set the Capture Compare4 Register value */
\r
2310 TIMx->CCR4 = Compare4;
\r
2314 * @brief Sets the TIMx Input Capture 1 prescaler.
\r
2315 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2316 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
\r
2317 * This parameter can be one of the following values:
\r
2318 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2319 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2320 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2321 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2324 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2326 /* Check the parameters */
\r
2327 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2328 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2329 /* Reset the IC1PSC Bits */
\r
2330 TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
\r
2331 /* Set the IC1PSC value */
\r
2332 TIMx->CCMR1 |= TIM_ICPSC;
\r
2336 * @brief Sets the TIMx Input Capture 2 prescaler.
\r
2337 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2338 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
\r
2339 * This parameter can be one of the following values:
\r
2340 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2341 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2342 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2343 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2346 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2348 /* Check the parameters */
\r
2349 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2350 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2351 /* Reset the IC2PSC Bits */
\r
2352 TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
\r
2353 /* Set the IC2PSC value */
\r
2354 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
\r
2358 * @brief Sets the TIMx Input Capture 3 prescaler.
\r
2359 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2360 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
\r
2361 * This parameter can be one of the following values:
\r
2362 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2363 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2364 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2365 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2368 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2370 /* Check the parameters */
\r
2371 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2372 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2373 /* Reset the IC3PSC Bits */
\r
2374 TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
\r
2375 /* Set the IC3PSC value */
\r
2376 TIMx->CCMR2 |= TIM_ICPSC;
\r
2380 * @brief Sets the TIMx Input Capture 4 prescaler.
\r
2381 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2382 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
\r
2383 * This parameter can be one of the following values:
\r
2384 * @arg TIM_ICPSC_DIV1: no prescaler
\r
2385 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
\r
2386 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
\r
2387 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
\r
2390 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
\r
2392 /* Check the parameters */
\r
2393 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2394 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
\r
2395 /* Reset the IC4PSC Bits */
\r
2396 TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
\r
2397 /* Set the IC4PSC value */
\r
2398 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
\r
2402 * @brief Sets the TIMx Clock Division value.
\r
2403 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2404 * @param TIM_CKD: specifies the clock division value.
\r
2405 * This parameter can be one of the following value:
\r
2406 * @arg TIM_CKD_DIV1: TDTS = Tck_tim
\r
2407 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
\r
2408 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
\r
2411 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
\r
2413 /* Check the parameters */
\r
2414 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2415 assert_param(IS_TIM_CKD_DIV(TIM_CKD));
\r
2416 /* Reset the CKD Bits */
\r
2417 TIMx->CR1 &= CR1_CKD_Mask;
\r
2418 /* Set the CKD value */
\r
2419 TIMx->CR1 |= TIM_CKD;
\r
2423 * @brief Gets the TIMx Input Capture 1 value.
\r
2424 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2425 * @retval Capture Compare 1 Register value.
\r
2427 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
\r
2429 /* Check the parameters */
\r
2430 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2431 /* Get the Capture 1 Register value */
\r
2432 return TIMx->CCR1;
\r
2436 * @brief Gets the TIMx Input Capture 2 value.
\r
2437 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2438 * @retval Capture Compare 2 Register value.
\r
2440 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
\r
2442 /* Check the parameters */
\r
2443 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2444 /* Get the Capture 2 Register value */
\r
2445 return TIMx->CCR2;
\r
2449 * @brief Gets the TIMx Input Capture 3 value.
\r
2450 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2451 * @retval Capture Compare 3 Register value.
\r
2453 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
\r
2455 /* Check the parameters */
\r
2456 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2457 /* Get the Capture 3 Register value */
\r
2458 return TIMx->CCR3;
\r
2462 * @brief Gets the TIMx Input Capture 4 value.
\r
2463 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2464 * @retval Capture Compare 4 Register value.
\r
2466 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
\r
2468 /* Check the parameters */
\r
2469 assert_param(IS_TIM_123458_PERIPH(TIMx));
\r
2470 /* Get the Capture 4 Register value */
\r
2471 return TIMx->CCR4;
\r
2475 * @brief Gets the TIMx Counter value.
\r
2476 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2477 * @retval Counter Register value.
\r
2479 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
\r
2481 /* Check the parameters */
\r
2482 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2483 /* Get the Counter Register value */
\r
2488 * @brief Gets the TIMx Prescaler value.
\r
2489 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2490 * @retval Prescaler Register value.
\r
2492 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
\r
2494 /* Check the parameters */
\r
2495 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2496 /* Get the Prescaler Register value */
\r
2501 * @brief Checks whether the specified TIM flag is set or not.
\r
2502 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2503 * @param TIM_FLAG: specifies the flag to check.
\r
2504 * This parameter can be one of the following values:
\r
2505 * @arg TIM_FLAG_Update: TIM update Flag
\r
2506 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2507 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2508 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2509 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2510 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2511 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2512 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2513 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2514 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2515 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2516 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2518 * - TIM6 and TIM7 can have only one update flag.
\r
2519 * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
\r
2520 * @retval The new state of TIM_FLAG (SET or RESET).
\r
2522 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2524 ITStatus bitstatus = RESET;
\r
2525 /* Check the parameters */
\r
2526 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2527 assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
\r
2529 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
\r
2535 bitstatus = RESET;
\r
2541 * @brief Clears the TIMx's pending flags.
\r
2542 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2543 * @param TIM_FLAG: specifies the flag bit to clear.
\r
2544 * This parameter can be any combination of the following values:
\r
2545 * @arg TIM_FLAG_Update: TIM update Flag
\r
2546 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
\r
2547 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
\r
2548 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
\r
2549 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
\r
2550 * @arg TIM_FLAG_COM: TIM Commutation Flag
\r
2551 * @arg TIM_FLAG_Trigger: TIM Trigger Flag
\r
2552 * @arg TIM_FLAG_Break: TIM Break Flag
\r
2553 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
\r
2554 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
\r
2555 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
\r
2556 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
\r
2558 * - TIM6 and TIM7 can have only one update flag.
\r
2559 * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
\r
2562 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
\r
2564 /* Check the parameters */
\r
2565 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2566 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
\r
2568 /* Clear the flags */
\r
2569 TIMx->SR = (uint16_t)~TIM_FLAG;
\r
2573 * @brief Checks whether the TIM interrupt has occurred or not.
\r
2574 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2575 * @param TIM_IT: specifies the TIM interrupt source to check.
\r
2576 * This parameter can be one of the following values:
\r
2577 * @arg TIM_IT_Update: TIM update Interrupt source
\r
2578 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2579 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2580 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2581 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2582 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2583 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2584 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2586 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2587 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
\r
2588 * @retval The new state of the TIM_IT(SET or RESET).
\r
2590 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2592 ITStatus bitstatus = RESET;
\r
2593 uint16_t itstatus = 0x0, itenable = 0x0;
\r
2594 /* Check the parameters */
\r
2595 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2596 assert_param(IS_TIM_GET_IT(TIM_IT));
\r
2598 itstatus = TIMx->SR & TIM_IT;
\r
2600 itenable = TIMx->DIER & TIM_IT;
\r
2601 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
\r
2607 bitstatus = RESET;
\r
2613 * @brief Clears the TIMx's interrupt pending bits.
\r
2614 * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
\r
2615 * @param TIM_IT: specifies the pending bit to clear.
\r
2616 * This parameter can be any combination of the following values:
\r
2617 * @arg TIM_IT_Update: TIM1 update Interrupt source
\r
2618 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
\r
2619 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
\r
2620 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
\r
2621 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
\r
2622 * @arg TIM_IT_COM: TIM Commutation Interrupt source
\r
2623 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
\r
2624 * @arg TIM_IT_Break: TIM Break Interrupt source
\r
2626 * - TIM6 and TIM7 can generate only an update interrupt.
\r
2627 * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
\r
2630 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
\r
2632 /* Check the parameters */
\r
2633 assert_param(IS_TIM_ALL_PERIPH(TIMx));
\r
2634 assert_param(IS_TIM_IT(TIM_IT));
\r
2635 /* Clear the IT pending Bit */
\r
2636 TIMx->SR = (uint16_t)~TIM_IT;
\r
2640 * @brief Configure the TI1 as Input.
\r
2641 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2642 * @param TIM_ICPolarity : The Input Polarity.
\r
2643 * This parameter can be one of the following values:
\r
2644 * @arg TIM_ICPolarity_Rising
\r
2645 * @arg TIM_ICPolarity_Falling
\r
2646 * @param TIM_ICSelection: specifies the input to be used.
\r
2647 * This parameter can be one of the following values:
\r
2648 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
\r
2649 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
\r
2650 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
\r
2651 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2652 * This parameter must be a value between 0x00 and 0x0F.
\r
2655 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2656 uint16_t TIM_ICFilter)
\r
2658 uint16_t tmpccmr1 = 0, tmpccer = 0;
\r
2659 /* Disable the Channel 1: Reset the CC1E Bit */
\r
2660 TIMx->CCER &= CCER_CC1E_Reset;
\r
2661 tmpccmr1 = TIMx->CCMR1;
\r
2662 tmpccer = TIMx->CCER;
\r
2663 /* Select the Input and set the filter */
\r
2664 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
\r
2665 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2666 /* Select the Polarity and set the CC1E Bit */
\r
2667 tmpccer &= CCER_CC1P_Reset;
\r
2668 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
\r
2669 /* Write to TIMx CCMR1 and CCER registers */
\r
2670 TIMx->CCMR1 = tmpccmr1;
\r
2671 TIMx->CCER = tmpccer;
\r
2675 * @brief Configure the TI2 as Input.
\r
2676 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2677 * @param TIM_ICPolarity : The Input Polarity.
\r
2678 * This parameter can be one of the following values:
\r
2679 * @arg TIM_ICPolarity_Rising
\r
2680 * @arg TIM_ICPolarity_Falling
\r
2681 * @param TIM_ICSelection: specifies the input to be used.
\r
2682 * This parameter can be one of the following values:
\r
2683 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
\r
2684 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
\r
2685 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
\r
2686 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2687 * This parameter must be a value between 0x00 and 0x0F.
\r
2690 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2691 uint16_t TIM_ICFilter)
\r
2693 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
\r
2694 /* Disable the Channel 2: Reset the CC2E Bit */
\r
2695 TIMx->CCER &= CCER_CC2E_Reset;
\r
2696 tmpccmr1 = TIMx->CCMR1;
\r
2697 tmpccer = TIMx->CCER;
\r
2698 tmp = (uint16_t)(TIM_ICPolarity << 4);
\r
2699 /* Select the Input and set the filter */
\r
2700 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
\r
2701 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
\r
2702 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
\r
2703 /* Select the Polarity and set the CC2E Bit */
\r
2704 tmpccer &= CCER_CC2P_Reset;
\r
2705 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
\r
2706 /* Write to TIMx CCMR1 and CCER registers */
\r
2707 TIMx->CCMR1 = tmpccmr1 ;
\r
2708 TIMx->CCER = tmpccer;
\r
2712 * @brief Configure the TI3 as Input.
\r
2713 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2714 * @param TIM_ICPolarity : The Input Polarity.
\r
2715 * This parameter can be one of the following values:
\r
2716 * @arg TIM_ICPolarity_Rising
\r
2717 * @arg TIM_ICPolarity_Falling
\r
2718 * @param TIM_ICSelection: specifies the input to be used.
\r
2719 * This parameter can be one of the following values:
\r
2720 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
\r
2721 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
\r
2722 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
\r
2723 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2724 * This parameter must be a value between 0x00 and 0x0F.
\r
2727 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2728 uint16_t TIM_ICFilter)
\r
2730 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2731 /* Disable the Channel 3: Reset the CC3E Bit */
\r
2732 TIMx->CCER &= CCER_CC3E_Reset;
\r
2733 tmpccmr2 = TIMx->CCMR2;
\r
2734 tmpccer = TIMx->CCER;
\r
2735 tmp = (uint16_t)(TIM_ICPolarity << 8);
\r
2736 /* Select the Input and set the filter */
\r
2737 tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
\r
2738 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
\r
2739 /* Select the Polarity and set the CC3E Bit */
\r
2740 tmpccer &= CCER_CC3P_Reset;
\r
2741 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
\r
2742 /* Write to TIMx CCMR2 and CCER registers */
\r
2743 TIMx->CCMR2 = tmpccmr2;
\r
2744 TIMx->CCER = tmpccer;
\r
2748 * @brief Configure the TI1 as Input.
\r
2749 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
\r
2750 * @param TIM_ICPolarity : The Input Polarity.
\r
2751 * This parameter can be one of the following values:
\r
2752 * @arg TIM_ICPolarity_Rising
\r
2753 * @arg TIM_ICPolarity_Falling
\r
2754 * @param TIM_ICSelection: specifies the input to be used.
\r
2755 * This parameter can be one of the following values:
\r
2756 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
\r
2757 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
\r
2758 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
\r
2759 * @param TIM_ICFilter: Specifies the Input Capture Filter.
\r
2760 * This parameter must be a value between 0x00 and 0x0F.
\r
2763 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
\r
2764 uint16_t TIM_ICFilter)
\r
2766 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
\r
2768 /* Disable the Channel 4: Reset the CC4E Bit */
\r
2769 TIMx->CCER &= CCER_CC4E_Reset;
\r
2770 tmpccmr2 = TIMx->CCMR2;
\r
2771 tmpccer = TIMx->CCER;
\r
2772 tmp = (uint16_t)(TIM_ICPolarity << 12);
\r
2774 /* Select the Input and set the filter */
\r
2775 tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
\r
2776 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
\r
2777 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
\r
2779 /* Select the Polarity and set the CC4E Bit */
\r
2780 tmpccer &= CCER_CC4P_Reset;
\r
2781 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
\r
2782 /* Write to TIMx CCMR2 and CCER registers */
\r
2783 TIMx->CCMR2 = tmpccmr2;
\r
2784 TIMx->CCER = tmpccer ;
\r
2799 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
\r